• List of Articles تأخیر

      • Open Access Article

        1 - Comparative Study Of late Payment Damage With Usury
        Babak Mohammad Rezapour Faezeh Jahani Moghadam
        In the world of exchanges and international trade which is based on the expansion of the banking system, the delayed payment penalty is accepted as a solution to the depreciation of the currency and also as a condition for the obligation to pay debts from customers in m More
        In the world of exchanges and international trade which is based on the expansion of the banking system, the delayed payment penalty is accepted as a solution to the depreciation of the currency and also as a condition for the obligation to pay debts from customers in most banking systems as well as in various legal rules. But this principle in Islamic countries has sometimes interfered with the concept of Reba, so that some jurists consider it as a Reba and have forbidden it. This principle has been widely debated in our country, but it has been accepted by the legislature as a principle. However, there are still many challenges regarding the legitimacy or lack of legitimacy of the principle of delayed payment penalty in the banking system. In this paper, it is attempted to address the reasons for the legitimacy of the delayed payment penalty in the banking system. Manuscript profile
      • Open Access Article

        2 - Model Reference Adaptive Control Design for a Teleoperation System with Output Prediction
        K. Hosseini-Sunny H. R. Momeni F. Janabi-Sharifi
        In this paper a new control scheme is proposed to ensure stability and performance of the teleoperation systems while a wide range of time delay of transmission line is allowed. For this mean, time delay is estimated and used to predict the plant output. A model referen More
        In this paper a new control scheme is proposed to ensure stability and performance of the teleoperation systems while a wide range of time delay of transmission line is allowed. For this mean, time delay is estimated and used to predict the plant output. A model reference adaptive controller (MRAC) is designed for the master site using the predicted output of the plant. The proposed control system indicates good stability and force tracking performance. For the slave site, an independent MRAC is designed and it is shown that a good tracking for the position and velocity signals is achieved. Manuscript profile
      • Open Access Article

        3 - Blind Source Separation of Speech Signals Using a One-Dimensional Block DUET Algorithm
        S. S. Fadaei M. H. Kahaei
        To separate speech signals using blind techniques, the DUET algorithm is used in which each source signal is separated by masking the mixed signals in the Time-Frequency domain. To do so, a two dimensional Histogram of mixed parameters is generated which is computationa More
        To separate speech signals using blind techniques, the DUET algorithm is used in which each source signal is separated by masking the mixed signals in the Time-Frequency domain. To do so, a two dimensional Histogram of mixed parameters is generated which is computationally burden, and thus, can not be used in real-time. In this paper, we introduce a new algorithm in which the separation process can be carried out online. Also, simulation results show that this algorithm has a comparable precision with respect to the DUET algorithm. Manuscript profile
      • Open Access Article

        4 - Simulation of Pyramidal Cells Firing Types and Adjustment of Their Characteristics by Means of Transient Potassium Currents
        Z. Daneshparvar M. R. Daliri
        Pyramidal cells of the dorsal cochlear nucleus (DCN) represent firing types with different latencies. They incorporate two transient potassium currents namely Ikif and Ikis with fast and slow inactivation gatings, respectively. Transient potassium currents i.e. currents More
        Pyramidal cells of the dorsal cochlear nucleus (DCN) represent firing types with different latencies. They incorporate two transient potassium currents namely Ikif and Ikis with fast and slow inactivation gatings, respectively. Transient potassium currents i.e. currents having both activation and inactivation gatings influence on the latency before firing. These currents cause different neural responses containing a regular firing, or a long latency before firing with or without a leading spike. In this paper, the firing behavior of DCN pyramidal cells is simulated first with a 3-variable conductance-based model. Next, mechanisms underlie neural responses of the model are analyzed by dynamical systems analysis methods. The model is a reduced version of Kanold and Manis model with 10 variables. Manuscript profile
      • Open Access Article

        5 - Analysis and Expansion of a Compact Model of Propagation Delay Time for Nano-CMOS NAND Gates in Response to Statistical Variability of Fabrication
        H.  Jooypa D. Dideban
        With shrinking transistor dimensions into nano meter scale, electrical parameters of transistors become more sensitive against statistical or random variations. Moreover, accurate estimation of these variations using “atomistic simulators” is time consuming and not a co More
        With shrinking transistor dimensions into nano meter scale, electrical parameters of transistors become more sensitive against statistical or random variations. Moreover, accurate estimation of these variations using “atomistic simulators” is time consuming and not a cost effective approach. In this paper for the first time, analytical models have been used to study the impacts of statistical variability of fabrication process on propagation delay time in a 35 nm CMOS NAND gate. With selecting appropriate set from analytical model’s parameters, the impact of statistical variability on the propagation delay time have been modeled and extended. Moreover, target analytical model has been benchmarked against statistical variability of fabrication process. The results obtained from extension of this model have been compared with the accurate atomistic simulations. It is observed that by applying different sets of parameters the maximum error of propagation delay time reaches to 8.7% against accurate atomistic simulations but by applying our proposed approach, Standard Deviation (SD) error of propagation delay is estimated to 2.4%. Also the SD error of propagation delay reaches to 9.9% when normal regenerated parameters have been used. Eventually using proposed algorithm which encompasses regenerated Gaussian parameters while taking the correlation factor into account, the SD error decreases to 1.6%. Manuscript profile
      • Open Access Article

        6 - Efficient Multicast Routing in Reconfigurable Networks-on-Chip
        F. Nasiri   Ahmad  Khademzadeh
        Several routing algorithms have been presented for multicast and unicast traffic in MPSoCs. Multicast protocols in NoCs are used for clock synchronization, cache coherency in distributed shared memory on-chip multiprocessors, replication and barrier synchronization. Uni More
        Several routing algorithms have been presented for multicast and unicast traffic in MPSoCs. Multicast protocols in NoCs are used for clock synchronization, cache coherency in distributed shared memory on-chip multiprocessors, replication and barrier synchronization. Unicast routing algorithms are not useful for multicast. Indeed, when unicast routing algorithms are employed to realize multicast operation, high traffic, congestion and deadlock are imposed to the network. To prevent from these problems, Tree-based and path based techniques have been proposed for multicast in multicomputers (and recently NoCs). In this paper, we present a new multicast routing method to decrease power consumption and multicast message latency based on a reconfigurable NoC architecture. In this line, we benefit from simple switches in our reconfigurable architecture instead of routers; we then divide the network to smaller partitions to make better trees for conducting multicast packets. Our evaluation results reveal that, for both real and synthetic traffic loads, the proposed method outperforms the baseline tree-based routing method in a reconfigurable mesh, and reduces message latency by up to 51% and power consumption by up to 33%. Manuscript profile
      • Open Access Article

        7 - Reducing OFF-State Current in Nano-Scale Double Gate Junctionless Field Effect Transistor (DGJL-FET) Using Doping Engineering of Channel Region
        S. Kalantari M. Vadizadeh
        Scaling the channel length leads to the increased leakage current of double gate junctionless field effect transistor (DGJL-FET) and, as a result, the increased power consumption in OFF-state. The present paper proposes a new structure for reducing the leakage current i More
        Scaling the channel length leads to the increased leakage current of double gate junctionless field effect transistor (DGJL-FET) and, as a result, the increased power consumption in OFF-state. The present paper proposes a new structure for reducing the leakage current in DGJL-FET, which is called modified DGJL-FET. In this structure, the channel doping under the gate is the same as the drain and source doping but higher than the mid-channel doping. The simulation results indicated that reducing the thickness of the doped layer under the gate, D, resulted in the reduced OFF-state current. For the proposed device with 10 nm channel length, the OFF-state current is less than that in the regular DGJL-FET by two orders of magnitude. Performance of the regular DGJL-FET and modified DGL-FET for different channel lengths is compared based on the IOFF/ION ratio, sub-threshold slope (SS), and intrinsic gate delay. For modified DGJL-FET, the mid-channel doping and Dare considered as additional parameters for improving the device’s performance in nanometer regime. The simulation results indicated that in the proposed device with channel length of 15 nm, values of SS and IOFF/ION ratio are improved compared to the regular DGJL-FET by 14% and 106 orders of magnitude, respectively. Manuscript profile
      • Open Access Article

        8 - Design of a New Observer for Unknown and Variable Input Time-Delay Estimation in Linear SISO Systems
        Hadi Chahkandi Nejad mohsen Farshad Ramazan Havangi
        In this paper, a novel observer is designed for online time delay estimation, in SISO linear systems, with variable and unknown time-delay in control input. It is clear that Laplace transfer function of a delayed system includes a time-delay operator (exponential and no More
        In this paper, a novel observer is designed for online time delay estimation, in SISO linear systems, with variable and unknown time-delay in control input. It is clear that Laplace transfer function of a delayed system includes a time-delay operator (exponential and non-rational). In this article, it is assumed that the only unknown and variable parameter in the system is the system’s time-delay. For designing the proposed observer, first, a Pade approximation is used for exponential operator of time delay to rationalize the system transfer function. Therefore, the new transfer function, which is an approximation of the main transfer function of the system, will include a time-variant delay parameter. After rewriting a state space realization of the mentioned transfer function and considering time delay parameter as an extra state variable, a system with nonlinear state equations will be formed. Eventually, using a Kalman filter, the systems states, such as system time-delay, are estimated. Finally, simulations results show rather desirable performance of the proposed estimator in dealing with unknown and variable time-delays. Manuscript profile
      • Open Access Article

        9 - Improvement in Electrical Characteristics of Silicon on Insulator Junctionless Field Effect Transistor (SOI-JLFET) Using the Auxiliary Gate
        M. Vadizadeh
        Silicon on insulator junctionless field effect transistor (SOI-JLFET) includes a single type doping at the same level in the source, channel, and drain regions. Therefore, its fabrication process is easier than inversion mode SOI-FET. However, SOI-JLFET suffers from hig More
        Silicon on insulator junctionless field effect transistor (SOI-JLFET) includes a single type doping at the same level in the source, channel, and drain regions. Therefore, its fabrication process is easier than inversion mode SOI-FET. However, SOI-JLFET suffers from high subthreshold slope (SS) as well as high leakage current. As a result, the SOI-JLFET device has limitation for high speed and low power applications. For the first time in this study, use of the auxiliary gate in the drain region of the SOI-JLFET has been proposed to improve the both SS and leakage current parameters. The proposed structure is called "SOI-JLFET Aug". The optimal selection for the auxiliary gate work function and its length, has improved the both SS and ION/IOFF ratio parameters, as compared to Regular SOI-JLFET. Simulation results show that, SOI-JLFET Aug with 20nm channel length exhibits the SS~71mV/dec and ION/IOFF~1013. SS and ON-state to OFF-state current (ION/IOFF) ratio of SOI-JLFET Aug are improved by 14% and three orders of magnitudes, respectively, as compared to the Regular SOI-JLFET. The SOI-JLEFT Aug could be good candidate for digital applications. Manuscript profile
      • Open Access Article

        10 - A Multigate Scheme to Improve CORPL under Traffic Load in Cognitive Radio Based Smart Grids with Mesh Topology
        S. A. Hashemian V. Tabatabvakili
        The conventional power grid has several drawbacks and a new powerful smart grid perspective has been recently introduced. The smart grid principle, allowing to efficiently manage an electrical grid network, needs to exploit a communication network for interconnecting t More
        The conventional power grid has several drawbacks and a new powerful smart grid perspective has been recently introduced. The smart grid principle, allowing to efficiently manage an electrical grid network, needs to exploit a communication network for interconnecting the Smart Grid devices. An increasing interest is toward wireless communications due to their higher flexibility. Within this context cognitive radio (CR) techniques has been introduced aiming to exploit more efficiently the radio spectrum resources. In neighborhood area network (NAN), mesh grids can be considered as one of possible network topologies. In such networks no base station is required and data will be sent to gateway by means of nodes themselves. Hence, routing is one of the main issues in such networks. Routing in such networks should be done by a protocol which maximizes throughput against cognitive radio drawbacks and Packets delay in such protocol needs to be minimum and suitable for smart grids applications. CORPL has been introduced as a routing protocol to meet some of these goals. In this paper by CORPL functionality would be evaluated under burst and poisson traffic. It will be shown that by increasing active nodes, CORPL functionality would be decreased. Then average upper limit for delay would be mathematically modeled and to reduce that a multigate scheme would be introduced. Manuscript profile
      • Open Access Article

        11 - Enhancing Speed, Area and Power Consumption of Carry Select Adders Using a New Grouping Structure
        A.  Mohammad Nezhad M.  Taghizadeh Firoozjaee
        Design of low-cost and high-speed datapath is very important for current computing systems. The adders are the essential parts of datapaths in computing systems. Among different types of adders, the carry select adder (CSeA) has a high speed while having the area overhe More
        Design of low-cost and high-speed datapath is very important for current computing systems. The adders are the essential parts of datapaths in computing systems. Among different types of adders, the carry select adder (CSeA) has a high speed while having the area overhead, as well. A factor influencing the speed of this adder is the incorporated grouping structure dependent to its components' delay. In this paper, at first, the delay and area of different existing CSeA architectures are reduced by utilizing a fast and small multiplexer. Then, a new grouping structure is proposed for more delay reduction based on a delay analysis. Implementation and experimental results show that applying the proposed grouping and modifications on different CSeA architectures leads to a high delay reduction in the add operation compared to the best existing grouping structure. For example, the amount of delay reduction in the investigated 32-bit CSeA architectures is more than 33%. In addition, the average reduction of power-delay-product criterion for 32-bit and 64-bit CSeAs utilizing the proposed grouping equals45% and 35%, respectively, compared to the CSeAs incorporating the current best grouping. Manuscript profile
      • Open Access Article

        12 - High Speed and Low Static Power Scan Cell Design in CMOS 22 nm
        P. Zakian R. Niaraki Asli
        One of the popular methods in design for testability (DFT) is scan design which leads on increase observability and controllability in circuit nodes. In this paper, we present a scan cell design which decreases the number of transistors, improves PDP and decreases energ More
        One of the popular methods in design for testability (DFT) is scan design which leads on increase observability and controllability in circuit nodes. In this paper, we present a scan cell design which decreases the number of transistors, improves PDP and decreases energy usage. The first proposed design is an optimized version of integrated low power gating scan cell, and the main idea of this design is reducing leakage current in the part of the circuit which is not used. Also, this design has the ability of reducing the propagation delay due to decreasing output parasitic capacitance. In the second proposed design, the scan cell is designed for controlling in pull down part of the inverter at slave latch so that static power consumption is diminished when current path is cut in unnecessary position. Simulations are carried out in 22 nm PTM technology CMOS by Hspice software. The results show that the proposed designs are superior to the previous designs considering propagation delay which is decreased, and enhanced static power consumption. Manuscript profile
      • Open Access Article

        13 - testDesign Decentralized Controller for a Group of Cooperative Robot to Pushing a Box in Presence of Network Constraints
        میلاد مرادی سید محمد مهدی Seyyed M. Mehdi Dehghan
        The problem of pushing objects by a group of cooperative robots has many applications on land and sea level and due to its importance, it has become a standard problem for evaluating various theories of robot cooperation. In this case, each robot produces distributed co More
        The problem of pushing objects by a group of cooperative robots has many applications on land and sea level and due to its importance, it has become a standard problem for evaluating various theories of robot cooperation. In this case, each robot produces distributed control force to push the object in the desired direction. The proposed methods for distributed control of an object on a time-varying path require information about the position of the robots relative to the object. The problem of the lack of sufficient knowledge of each robot of how the robots are positioned relative to the body can be solved by proposing a consensus issue on positional moments. In this case, the robots must reach a consensus on these moments by exchanging information through the communication network between them. The effect of communication network between robots on the process of reaching consensus and the effect of delay in consensus on the results of control of object on the desired path is the subject of this article. In this paper, the appropriate control law for achieving consensus in the absence of full connection between all bots, delay and the probability of data loss in the communication network is presented. The maximum allowable network delay is also specified to prevent the instability of object motion control. The simulation results show the capability of the proposed method for controlling the velocity of the object on the desired variable path and show the effect of network constraints on the performance of the controller. Manuscript profile
      • Open Access Article

        14 - Detection and Mitigation of a Combined Cyber Attack on Automatic Generation Control
        Tina Hajiabdollah H. Seifi Hamed Delkhosh
        Recent advances in power system monitoring and control require communication infrastructure to send and receive measurement data and control commands. These cyber-physical interactions, despite increasing efficiency and reliability, have exposed power systems to cyber a More
        Recent advances in power system monitoring and control require communication infrastructure to send and receive measurement data and control commands. These cyber-physical interactions, despite increasing efficiency and reliability, have exposed power systems to cyber attacks. The Automatic Generation Control (AGC) is one of the most important control systems in the power system, which requires communication infrastructure and has been highly regarded by cyber attackers. Since a successful attack on the AGC, not only has a direct impact on the system frequency, but can also affect the stability and economic performance of the power system. Therefore, understanding the impact of cyber attacks on AGC and developing strategies to defend against them have necessity and research importance. In most of the research in the field of attack-defense of AGC, the limitations of AGC in modeling such as governor dead band and communication network transmission delay have been ignored. On the other hand, considering two cyber attacks on the AGC and proposing a way to defend against them simultaneously, have not been considered. In this paper, while using the improved AGC model including governor dead band and communication network transmission delay, the effect of two attacks - data injection attack (FDI) and delay attack which are the most important cyber attacks on AGC - has been investigated. Also, the simultaneous effect of these two attacks is discussed as a combined cyber attack. The Kalman filter-based three-step defense method has been proposed to detect, estimate and mitigate the impact of the attacks and its effectiveness has been tested on the two-area AGC system. Manuscript profile
      • Open Access Article

        15 - Robust Finite-Time Chattering Free Sliding Mode Adaptive Impedance controller in Remote Control System in Presence of Random Delay
        Abolfazl Kamali Ardakani Hadi Safdarkhani
        Remote control of robots is one of the most relevant and practical fields in robotics. Most of the control structures of remote operation systems seek to achieve transparency and stability at the same time, which the simultaneous achievement of the both, considering the More
        Remote control of robots is one of the most relevant and practical fields in robotics. Most of the control structures of remote operation systems seek to achieve transparency and stability at the same time, which the simultaneous achievement of the both, considering the uncertainty and disturbances in the system and random delay in the communication channel is very challenging. So far, many researchers have used position, speed, force or impedance information to provide various control methods, but none of these methods have achieved complete transparency and robust stability in the presence of random delay and uncertainties and disturbances and compromises between them should be made. In this paper, using a new method, a control structure including sliding mode control, adaptive control and impedance control is presented. This method has been simulated by Simulink of MATLAB software and it has been shown that this method is able to establish ideal transparency and ensure robust stability in the system with disturbances and uncertainties in the presence of random delay in the network. Manuscript profile
      • Open Access Article

        16 - Load Balancing in Fog Nodes using Reinforcement Learning Algorithm
        niloofar tahmasebi pouya Mehdi-Agha  Sarram
        Fog computing is an emerging research field for providing cloud computing services to the edges of the network. Fog nodes process data stream and user requests in real-time. In order to optimize resource efficiency and response time, increase speed and performance, task More
        Fog computing is an emerging research field for providing cloud computing services to the edges of the network. Fog nodes process data stream and user requests in real-time. In order to optimize resource efficiency and response time, increase speed and performance, tasks must be evenly distributed among the fog nodes. Therefore, in this paper, a new method is proposed to improve the load balancing in the fog computing environment. In the proposed algorithm, when a task is sent to the fog node via mobile devices, the fog node using reinforcement learning decides to process that task itself, or assign it to one of the neighbor fog nodes or cloud for processing. The evaluation shows that the proposed algorithm, with proper distribution of tasks between nodes, has less delay to tasks processing than other compared methods. Manuscript profile
      • Open Access Article

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        ابراهیم عبدی
      • Open Access Article

        18 - Reduction of network load by mapping the application in the network on a chip using the discrete Harris hawk algorithm
        Elham Hajebi Vahid Sattari-Naeini
        Reducing load and power consumption in on-chip network systems is very important and one of the most important issues to increase the efficiency of on-chip network is the issue of mapping an application on the chip network. Solving the application mapping problem to fin More
        Reducing load and power consumption in on-chip network systems is very important and one of the most important issues to increase the efficiency of on-chip network is the issue of mapping an application on the chip network. Solving the application mapping problem to find the best mapping is a complex and time consuming issue and has a huge impact on network latency and power consumption. In this paper, using the Harris hawk algorithm, we have been able to provide a method for mapping processing cores to the network on chip to reduce the load on the network and thus congestion in the links and improve network performance. The simulation results show that this algorithm performs better than the basic algorithms. Manuscript profile
      • Open Access Article

        19 - An Algorithm for Optimal Control of a Class of Linear Time Varying Systems with Computational Time Reduction and Increasing Its Speed Approach in Engineering Problems
        Mehdi Yousefi Tabari Zahra Rahmani Ali Vahidian Kamyad Seyed Jalil Sadati
        Time-delay systems have been very much considered in the last few decades. Many of these time-delay systems appear in different systems and branches of science such as engineering, chemistry, physics, disease models. The presence of delay makes the analysis and control More
        Time-delay systems have been very much considered in the last few decades. Many of these time-delay systems appear in different systems and branches of science such as engineering, chemistry, physics, disease models. The presence of delay makes the analysis and control of such systems much more complicated. In fact, the application of Pontryagin’s maximum principle to the optimal control problems with time-delay results in boundary value problem involving both delay and advance terms. In this paper, we consider a time-delay optimal control problems. The first section, using the Pontryagin's maximum principle for optimal control problems with time delay, the necessary optimality conditions for this problem, are obtained. Then a new algorithm is proposed to solve this problem numerically. This algorithm is based on an approximation for derivatives and linear interpolation for delayed arguments. Finally, the resulting equations becomes a linear programming problem that can be solved numerically. The efficiency of the proposed method is evaluated by solving several numerical examples. Manuscript profile
      • Open Access Article

        20 - Bounded Delays in Switching Signal for Switched Affine Systems
        Arman Sehatnia F. Hashemzadeh Mahdi Baradarannia
        In this article, the consequence of the presence of delay in the switch signal for switched affine systems is investigated. First, based on the principles of stability, the process of extracting the switch law as the only control input is examined, then by presenting th More
        In this article, the consequence of the presence of delay in the switch signal for switched affine systems is investigated. First, based on the principles of stability, the process of extracting the switch law as the only control input is examined, then by presenting the practical stability issue for switched systems, more realistic view of these systems is proposed. The main focus of the article will be on the effect of delay in the transmission of switching signal information. The presence of limited delay in switching signal is usually caused by high volume of switching law calculations or any cyber attacks. In this paper, the practical Lyapunov stability results related to the states before and after the presence of delay in switching signal for a linear switched affine system are compared analytically and simulated. The results of the comparison of these modes show that when the value of delay in switching signal increases, the ultimate limit of the error for system states becomes larger, and this means a decrease in the convergence of the system states. In this regard, the results implemented for a DC-DC power converter and the necessary comparisons are presented in the last chapter. Manuscript profile