Enhancing Speed, Area and Power Consumption of Carry Select Adders Using a New Grouping Structure
Subject Areas : electrical and computer engineeringA. Mohammad Nezhad 1 , M. Taghizadeh Firoozjaee 2
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Keywords: Carry select adderbasic groupingsadder delaypower consumption,
Abstract :
Design of low-cost and high-speed datapath is very important for current computing systems. The adders are the essential parts of datapaths in computing systems. Among different types of adders, the carry select adder (CSeA) has a high speed while having the area overhead, as well. A factor influencing the speed of this adder is the incorporated grouping structure dependent to its components' delay. In this paper, at first, the delay and area of different existing CSeA architectures are reduced by utilizing a fast and small multiplexer. Then, a new grouping structure is proposed for more delay reduction based on a delay analysis. Implementation and experimental results show that applying the proposed grouping and modifications on different CSeA architectures leads to a high delay reduction in the add operation compared to the best existing grouping structure. For example, the amount of delay reduction in the investigated 32-bit CSeA architectures is more than 33%. In addition, the average reduction of power-delay-product criterion for 32-bit and 64-bit CSeAs utilizing the proposed grouping equals45% and 35%, respectively, compared to the CSeAs incorporating the current best grouping.
[1] B. Parhami, Computer Arithmetic: Algorithms and Hardware Designs, 2nd Ed. New York, NY, USA: Oxford Univ. Press, 2010.
[2] Z. Chen and I. Koren, "Techniques for yield enhancement of VLSI adders," in Proc. Int. Conf. Appl. Specific Array Process., pp. 222-229, Strasbourg, France, 24-26 Jul. 1995.
[3] O. J. Bedrij, "Carry-select adder," IRE Trans. on Electronic Computers, vol. 11, no. 3, pp. 340-346, Jun. 1962.
[4] M. A. Akbar and J. Lee, "Self-repairing adder using fault localization," Microelectronics Reliability, vol. 54, no. 6-7, pp. 1443-1451, Jun./Jul. 2014.
[5] J. M. Rabaey, Digital Integrated Circuits-A Design Perspective, Prentice Hall Press, 2001.
[6] Y. Kim and L. S. Kim, "64-bit carry-select adder with reduced area," Electronics Letters, vol. 37, no. 10, pp. 614-615, May 2001.
[7] Y. He, C. H. Chang, and J. Gu, "An area-efficient 64-bit square root carry-select adder for low power application," in Proc. IEEE Int. Symp. Circuits and Systems, pp. 4082-4085, Kobe, Japan, 23-26 May 2005.
[8] U. S. Kumar, K. K. M. Salih, and K. Sajith, "Design and implementation of carry select adder without using multiplexers," in Proc. Int. Conf. on Emerging Technology Trends in Electronics, Communication and Networking, 5 pp., Gujarat, India, 19-21 Dec. 2012.
[9] B. Ramkumar and H. M. Kittur, "Low-power and area-efficient carry select adder," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 20, no. 2, pp. 371-375, Feb. 2012.
[10] I. C. Wey, C. C. Ho, Y. S. Lin, and C. C. Peng, "An area-efficient carry select adder design by sharing the common Boolean logic term," in Proc. Int. Multiconference of Engineering and Computer Scientist, IMECS'12, vol. 2, pp. 1091-1094, Hong Kong, Hong Kong, 14-16 Mar. 2012.
[11] S. Manju and V. Sornagopal, "An efficient SQRT architecture of carry select adder design by common Boolean logic," in Proc. IEEE Int. Conf. on Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System, 5 pp., Tiruvannamalai, India, 7-9 Jan. 2013.
[12] G. K. Reddy and D. S. B. Rao, "A comparative study on low-power and high speed carry select adder," in Proc. IEEE 9th Int. Conf. on Intelligent Systems and Control, ISCO'15, 7 pp., oimbatore, India, 9-10 Jan. 2015.
[13] B. K. Mohanty and S. K. Patel, "Area-delay-power efficient carry-select adder," IEEE Trans. Circuits and Systems-II: Express Briefs, vol. 61, no. 6, pp. 418-422, Jun. 2014.
[14] M. Bahadori, M. Kamal, A. Afzali-Kusha, and M. Pedram, "An energy and area efficient yet high-speed square-root carry select adder structure," Computers & Electrical Engineering, vol. 58, pp. 101-112, Feb. 2017.
[15] N. H. E. Weste and K. Eshraghian, Principle of CMOS VLSI Design: A Systems Perspective, Pearson Education, 3rd Edition, 2005.
[16] D. P. Vasudevan, P. K. Lala, and J. P. Parkerson, "Self-checking carry-select adder design based on two-rail encoding," IEEE Trans. Circuits and Systems I: Regular Papers, vol. 54, no. 12, pp. 2696-2705, Dec. 2007.
