Reduction of network load by mapping the application in the network on a chip using the discrete Harris hawk algorithm
Subject Areas :
Elham Hajebi
1
(Department of Computer Engineering)
Vahid Sattari-Naeini
2
()
Keywords: Network-on-chip, Core-mapping, Latency, Utilization of link, HHO,
Abstract :
Reducing load and power consumption in on-chip network systems is very important and one of the most important issues to increase the efficiency of on-chip network is the issue of mapping an application on the chip network. Solving the application mapping problem to find the best mapping is a complex and time consuming issue and has a huge impact on network latency and power consumption. In this paper, using the Harris hawk algorithm, we have been able to provide a method for mapping processing cores to the network on chip to reduce the load on the network and thus congestion in the links and improve network performance. The simulation results show that this algorithm performs better than the basic algorithms.
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