A 2-bit Full Comparator Design with Minimum Quantum Cost Function in Quantum-Dot Cellular Automata
Subject Areas : Electromagnetic, Antenna and PropagationDavoud Bahrepour 1 , Negin Maroufi 2
1 - Islamic Azad University, Mashhad Branch
2 - Khorasan Razavi, Science and Research Branch, Islamic Azad University
Keywords: Quantum-Dot Cellular Automata, , Full Comparator, , Cost Function, , QCA Cell, , Majority Gate, , NOT Gate, ,
Abstract :
In recent years, reduction of the complementary metal-oxide-semiconductor (CMOS) circuit feature size has caused significant challenges, such as current loss and leakage, and high power consumption. Therefore, further reduction of the size of CMOS technology is not feasible. Quantum-dot cellular automata (QCA) is an emerging technology at the nanoscale, which can utilize for designing computers and very-large-scale integration (VLSI) circuits in the near future. QCA technology makes it possible to design low-power, high-performance, and area-efficient logical circuits. A comparator function is a digital logical function, which compares whether a bit is greater than, smaller than or equal to the other bit or not (half comparator). Full comparator has a third input, which shows the result of the previous step. Half and full comparators play an essential role in CPU architecture. In this paper, a full comparator circuit based on the QCA and a new quantum cost function is proposed. Besides a 2-bit comparator is presented based on the introduced full comparator. Using the new quantum cost function the proposed full comparator design is compared with the previously presented designs in terms of area, delay, and complexity. Comparisons show that the proposed design has less area and delay and therefore, it is more suitable for utilizing in CPU design.
[1] J. C. Das, and D. De, "Novel low power reversible binary incrementer design using quantum-dot cellular automata. Microprocessors and Microsystems", vol. 42, 2016, pp. 10-23.
[2] R. Jayalakshmi, and R. Amutha, "A Theoretical Study on the Implementation of Quantum Dot Cellular Automata", Fourth International Conference on Advances in Electrical, Electronics, Information, Communication, and Bio-Informatics (AEEICB), Chennai, 2018, pp. 1-6.
[3] R. Sarma, and R. Jain, "Quantum Gate Implementation of a Novel Reversible Half Adder and Subtractor Circuit," International Conference on Intelligent Circuits and Systems (ICICS), Phagwara, 2018, pp. 72-76.
[4] M. M. Rahman, N. M. Nahid, and M. K. Hassan, "Energy dissipation dataset for reversible logic gates in quantum dot-cellular automata" Data in brief, vol. 10, 2017, pp. 557-560.
[5] M. Walter, R. Wille, D. Grobe, F. S. Torres, and R. Drechsler, "An exact method for design exploration of quantum-dot cellular automata," Design, Automation and Test in Europe Conference and Exhibition (DATE), Dresden, 2018, pp. 503-508.
[6] V. S. Kalogeiton, D. P. Papadopoulos, O. Liolis, V. A. Mardiris, G. C. Sirakoulis, and I. G. Karafyllidis, "Programmable Crossbar Quantum-Dot Cellular Automata Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 8, 2017, pp. 1367-1380.
[7] G. Cocorullo, P. Corsonello, F. Frustaci and S. Perri, "Design of Efficient BCD Adders in Quantum-Dot Cellular Automata," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 5, 2017, pp. 575-579.
[8] M. Mohammadi, S. Gorgin and M. Mohammadi, "Design of non-restoring divider in quantum-dot cellular automata technology," IET Circuits, Devices and Systems, vol. 11, no. 2, 2017, pp. 135-141.
[9] K. Walus, T. J. Dysart, G. A. Jullien, and R. A. Budiman, "QCADesigner: A rapid design and simulation tool for quantum-dot cellular automata," IEEE transactions on nanotechnology, vol. 3, no. 1, 2004, pp. 26-31.
[10] D. Bahrepour, and J. Forouzanfar, "A Novel Robust Macrocell Based on Quantum Dot Cellular Automata. Quantum Matter," vol. 5, no. 5, 2016, pp. 689-696.
[11] P. D. Tougaw, and C. S. Lent, "Logical devices implemented using quantum cellular automata," Journal of Applied Physics, vol. 75, no. 3, 1994, pp. 1818-1825.
[12] D. Bahrepour, "A Novel Full Comparator Design Based on Quantum-Dot Cellular Automata. International Journal of Information and Electronics Engineering," vol. 5, no. 6, 2015, pp. 406.
[13] S. Hashemi, M. Tehrani, and K. Navi, "An efficient quantum-dot cellular automata full-adder. Scientific Research and Essays," vol. 7, no. 2, 2012, pp. 177-189.
[14] S. S. Anuradha, B. D. Ravi, and M. Pasar Vishal, "Design of five input majority gate full comparator using Quantum-Dot Cellular Automata," International Journal of Ethics in Engineering and Management Education, vol. 1, no. 4, 2014, pp. 326-328.
[15] Y. Xia, and K. Qiu, "Design and application of universal logic gate based on quantum-dot cellular automata" In Communication Technology, ICCT. 11th IEEE International Conference on, 2008, pp. 335-338.
[16] S. Perri, P. Corsonello, and G. Cocorullo, "Design of efficient binary comparators in quantum-dot cellular automata," IEEE Transactions on Nanotechnology, vol. 13, no. 2, 2014, pp. 192-202.
[17] M. Gladshtein, "Quantum-dot cellular automata serial decimal adder," IEEE Transactions on Nanotechnology, vol. 10, no. 6, 2011. pp. 1377-1382.
[18] S. Saravanan, I. Vennila, and S. Mohanram, "Design and Implementation of an Efficient Reversible Comparator Using TR Gate," Circuits and Systems, vol. 7, no. 9, 2016, pp. 2578.
[19] M. J. Sharifi, and D. Bahrepour, "Introducing a technology index concept and optimum performance design procedure for single-electron-device based circuits," Microelectronics Journal, vol. 42, no. 7, 2011, pp. 942-949.
[20] M. Chabi, A. Roohi, R. F. DeMara, S. Angizi, K. Navi, and H. Khademolhosseini, "Cost-efficient QCA reversible combinational circuits based on a new reversible gate," In Computer Architecture and Digital Systems (CADS), 18th CSI International Symposium on, 2015, pp. 1-6.
[21] Oklobdzija, V. G. (Ed.). (2001). The computer engineering handbook. CRC press.
