List of Articles Majority Gate

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  1 - A 2-bit Full Comparator Design with Minimum Quantum Cost Function in Quantum-Dot Cellular Automata
  Davoud Bahrepour Negin Maroufi
  10.7508/jist.2018.04.002
  In recent years, reduction of the complementary metal-oxide-semiconductor (CMOS) circuit feature size has caused significant challenges, such as current loss and leakage, and high power consumption. Therefore, further reduction of the size of CMOS technology is not feas More

  In recent years, reduction of the complementary metal-oxide-semiconductor (CMOS) circuit feature size has caused significant challenges, such as current loss and leakage, and high power consumption. Therefore, further reduction of the size of CMOS technology is not feasible. Quantum-dot cellular automata (QCA) is an emerging technology at the nanoscale, which can utilize for designing computers and very-large-scale integration (VLSI) circuits in the near future. QCA technology makes it possible to design low-power, high-performance, and area-efficient logical circuits. A comparator function is a digital logical function, which compares whether a bit is greater than, smaller than or equal to the other bit or not (half comparator). Full comparator has a third input, which shows the result of the previous step. Half and full comparators play an essential role in CPU architecture. In this paper, a full comparator circuit based on the QCA and a new quantum cost function is proposed. Besides a 2-bit comparator is presented based on the introduced full comparator. Using the new quantum cost function the proposed full comparator design is compared with the previously presented designs in terms of area, delay, and complexity. Comparisons show that the proposed design has less area and delay and therefore, it is more suitable for utilizing in CPU design. Manuscript profile
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  2 - Design of an Efficient XOR Circuit in Nanomagnetic Logic
  Samira Sayedsalehi Z. Azadi Motlag
  The aim of this paper is to suggest new and efficient designs for XOR circuits based on nanomagnetic logic technology in order to implementation of nanomagnetic computational circuits such as adders, subtractors and multipliers. Nanomagnetic logic due to its properties More

  The aim of this paper is to suggest new and efficient designs for XOR circuits based on nanomagnetic logic technology in order to implementation of nanomagnetic computational circuits such as adders, subtractors and multipliers. Nanomagnetic logic due to its properties such as very high speed, low power consumption, scalability and working on room temperature is a suitable alternative for conventional transistor technology. First, nanomagnetic majority gates are introduced then two efficient designs with minimum area, minimum number of nanomagnetic elements and lowest delays for XOR circuits are proposed based on a three-input minority gate and a five-input majority gate. Basic elements in these designs are out-of-plane nanomagnetic cells made of Co/Pt, due to relative advantages of this alloy. Clocking field which is an external uniform magnetic field is required for proper performance of these proposed circuits. MagCAD tool was used for implementation of these designs, and the accuracy of operation of these circuits was proved by applying Modelsim simulator. According to the results of this simulation, it is shown that the proposed single layer and multilayer three-input XOR gates have improvement in comparison to the state-of-art design in number of gates 50% and 25%, in delay 80% and 80%, and in the number of elements 23% and 21%, respectively. Manuscript profile