List of Articles Ternary Circuits

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  1 - Design of Quantum Reversible Ternary Multiplexer and Demultiplexer Circuits
  M. Haghparast A. Taheri Monfared
  Multiplexer and demultiplexer circuits are among the main circuits in designing the complicated hardware. Therefore, enhancing their performance is very important. In the last few years one of the cases that got the attention of the researchers is designing circuits wit More

  Multiplexer and demultiplexer circuits are among the main circuits in designing the complicated hardware. Therefore, enhancing their performance is very important. In the last few years one of the cases that got the attention of the researchers is designing circuits with low power. Using the reversible logic in designing the circuits can reduce power dissipation and power consumption. Using the ternary logic also leads to a better performance, reducing the power consumption and enhancing of fault tolerance in reversible circuits. In this paper, we have presented quantum reversible ternary multiplexer and demultiplexer circuits, we have used reversible ternary shift and controlled Feynman gates. Presented circuits in this paper have a better performance in compared to the previous designs. The improvements are reported. Manuscript profile
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  2 - Design of New Ternary Flip Flops Using CNTFET in Nanotechnology
  katayoun rahbari seyed ali hosseinoi
  Using multi-valued logic can reduce chip interconnections, which can have a direct effect on chip area and interconnections power consumption. In recent years, due to the ability of Nano electronics in the design of multi-level circuits, research in this field has flour More

  Using multi-valued logic can reduce chip interconnections, which can have a direct effect on chip area and interconnections power consumption. In recent years, due to the ability of Nano electronics in the design of multi-level circuits, research in this field has flourished. The sequential circuits, flip-flops are important components of processors and VLSI circuits. In this paper, for the first time, a ternary flip-flop with a pulse generator has been proposed, and also a ternary binary-decode flip-flop and the first flip-flop using a buffer have been introduced. Then these flip-flops are compared with themselves and previous circuits. Also, these flip-flops have been used in the design of the ternary counter. The simulation results with HSPICE software show the correct performance of the proposed circuits. There is a 20% improvement in delay and a reduction in the number of transistors in the STI pulse generator flip-flop model, 30% in the SP flip-flop, and 30% in the buffer flip-flop. Also, in the comparison table, the advantages and disadvantages of each have been examined. Manuscript profile