Analysis of Slew Rate and Settling Time in Two Stage CMOS Operational Amplifiers with Cascode Compensation
Subject Areas : electrical and computer engineeringhannane Gholamntaj 1 , habib Adarang 2 , seyed saleh Mohseni 3 , seyed saleh Ghoreishi 4
1 -
2 -
3 -
4 -
Keywords: Settling time, slew rate, slewing, cascode compensation, operational amplifier, step response,
Abstract :
Slew rate and settling time are the important parameters in opamps with feedback. In this paper, the slew rate and settling time of the fully differential two stages folded cascade architecture amplifier with cascade compensation is analyzed. An important characteristic of the proposed analytical model is that the behavior of the transistors is examined in detail after applying the step in the input, and it is shown that the settling time as well as slew rate would depend on the size of the input step. The performed analysis can be beneficial for design and manual calculations in integrated circuits. Moreover, circuit level simulation is used to validate the analytical results with particular emphasis on slew rate and settling time. Simulations results show excellent conformance between the analytical equations and the simulation results.
[1] F. Wang and R. Harjani, "An improved model for the slewing behavior of opamps," IEEE Trans. on Circuits and Systems II, vol. 42, no. 10, pp. 679-681, Oct. 1995.
[2] M. Yavari, N. Maghari, and O. Shoaei, "An accurate analysis of slew rate for two-stage CMOS opamps," IEEE Trans. on Circuits and Systems II, vol. 52, no. 3, pp. 164-167, Mar. 2005.
[3] H. Rezaee-Dehsorkh, N. Ravanshad, R. Lotfi, and K. Mafinezhad, "Modified model for settling behavior of operational amplifiers in nanoscale CMOS," IEEE Trans. on Circuits and Systems II, vol. 56, no. 5, pp. 384-388, May 2009.
[4] D. G. Nairn, "Cascode loads and amplifier settling behavior," IEEE Trans. on Circuits and Systems I, vol. 59, no. 1, pp. 44-51, May/Jan. 2012.
[5] Z. Yan, P. Mak, M. Law, R. Martins, and F. Maloberti, "Nested-current-mirror rail-to-rail-output single-stage amplifier with enhancements of DC gain, GBW and slew rate," IEEE J. of Solid State Circuits, vol. 50, no. 10, pp. 2353-2366, Oct. 2015.
[6] S. Seth and B. Murmann, "Settling time and noise optimization of a three-stage operational transconductance amplifier," IEEE Trans. on Circuits and Systems I, vol. 60, no. 5, pp. 1168-1174, May 2013.
[7] G. Giustolisi and G. Palumbo, "Three-stage dynamic-biased CMOS amplifier with a robust optimization of the settling time," IEEE Trans. on Circuits and Systems I, vol. 62, no. 11, pp. 2641-2651, Nov. 2015.
[8] G. Giustolisi and G. Palumbo, "Design of three-stage OTA based on settling-time requirements including large and small signal behavior," IEEE Trans. on Circuits and Systems I, vol. 68, no. 3, pp. 998-1011, Mar. 2021.
[9] M. Liu, D. Li, and Z. Zhu, "A dual-supply two-stage CMOS op-amp for high-speed pipeline ADCs application," IEEE Trans. on Circuits and Systems II, vol. 67, no. 4, pp. 650-654, Apr. 2020.
[10] A. Paul, J. Ramirez-Angulo, A. J. Lopez-Martin, R. G. Carvajal, and J. M. Rocha-Perez, "Pseudo-three-stage miller op-amp with enhanced small-signal and large-signal performance," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 10, pp. 2246-2259, Oct. 2019.
[11] C. Chanapromma and J. Mahattanakul, "Improved design procedure for two-stage CMOS op-amp employing current buffer," in Proc. IEEE 17th Int. Conf. on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, pp. 384-387, Phuket, Thailand, 24-27 Jun. 2020.
[12] A. Gupta and S. Singh, "Design of two stage CMOS op-amp with high slew rate and high gain in 180 nm," in Proc. IEEE 2nd Int. Conf. on I-SMAC, pp. 341-345, Palladam, India, 30-31 Aug.. 2018.
[13] C. Chanapromma and J. Mahattanakul, "Redesign procedure for two-stage CMOS op-amp with least error of frequency response and phase margin," in Proc. IEEE 17th Int. Conf. on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology, pp. 717-720, Phuket, Thailand, 24-27 Jun. 2020.
[14] R. Lotfi, M. Taherzadeh-Sani, M. Yaser Azizi, and O. Shoaei, "Low-power design techniques for low-voltage fast-settling operational amplifiers in switched-capacitor applications," Integration, vol. 36, no. 4, pp. 175-189, Nov. 2003.
[15] T. C. Carusone, D. A. Johns, and K. W. Martin, Analog Integrated Circuit Design, 2nd Edition, John Wiley & Sons Inc., 2012.