Evaluating Schottky-Barrier-Type GNRFETs-Based Static Flip-Flop Characteristic under Manufacturing Process Parameters Variations
Subject Areas : electrical and computer engineeringErfan Abbasian 1 , Morteza Gholipour 2
1 -
2 - Babol Noshirvani University of Technology
Abstract :
Graphene nanoribbon field-effect transistors (GNRFETs) have emerged as encouraging replacement candidate for traditional silicon-based transistor in next-generation technology. Since GNRFETs’ channel is about a few nanometers, impact of manufacturing process variations on circuits’ performance is very large. In this paper, impact of manufacturing process variations such as oxide thickness, channel length, and number of dimer lines on schottky-barrier-type GNRFETs (SB-GNRFETs)-based static flip-flop characteristics such as delay, power, and energy-delay-product (EDP) is evaluated and analyzed. Furthermore, Monte-Carlo (MC) simulations have been performed for statistical analysis of these variations. With change in the oxide thickness from its nominal value to 1.15 nm, the propagation delay and EDP are increased by 31.57% and 60.62%, respectively. Also, the channel length variation has the least effect on flip-flop characteristic. The propagation delay and EDP are increased by 315.48 % and 204.79%, respectively, when the number of dimer lines increases by one from its nominal value. The results obtained from MC simulations show that the oxide thickness variations lead to spread of 2.46, 1.57 and 2.39 times higher than the number of dimer lines variations in histogram distribution of flip-flop characteristic.
[1] L. B. Kish, "End of Moore's law: thermal (noise) death of integration in micro and nano electronics," Physics Letters A, vol. 305, no. 3, pp. 144-149, Dec. 2002.
[2] F. Kreupl, "Advancing CMOS with carbon electronics," in Proc. of Conf. on Design, Automation & Test in Europe, 6 pp., Dresden, Germany, 24-28 Mar. 2014.
[3] S. Narendra, V. De, S. Borkar, D. A. Antoniadis, and A. P. Chandrakasan, "Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18 µm CMOS," IEEE J. of Solid-State Circuits, vol. 39, no. 3, pp. 501-510, Mar. 2004.
[4] H. R. Aradhya, H. Madan, T. Megaraj, M. Suraj, R. Karthik, and R. Muniraj, "GNRFET based 8-bit ALU," International J. of Electronics and Communication Engineering, vol. 5, no. 1, pp. 45-54, Dec. 2016.
[5] A. Y. Goharrizi, M. Pourfath, M. Fathipour, and H. Kosina, "Device performance of graphene nanoribbon field-effect transistors in the presence of line-edge roughness," IEEE Trans. on Electron Devices, vol. 59, no. 12, pp. 3527-3532, Dec. 2012.
[6] S. Joshi and U. Albalawi, "Statistical process variation analysis of schottky-barrier type GNRFET for RF application," in Proc. Int. Conf. on Current Trends in Computer, Electrical, Electronics and Communication, 6 pp., Mysore, India, 8-9 Sept. 2016.
[7] A. Sangai, Circuit Level Delay and Power Analysis of Graphene Nano-Ribbon Field-Effect Transistors Using Monte Carlo Simulations and Standard Cell Library Characterization, MSc Thesis, University of Illinios-Urbana-Champaign, 2014.
[8] International Technology Roadmap for Semiconductors (ITRS), http://www.itrs.net/, 2013.
[9] F. Schwierz, "Graphene transistors," Nature Nnanotechnology, vol. 5, no. 7, pp. 487-496, May 2010.
[10] K. S. Novoselov, A. K. Geim, S. V. Morozov, D. Jiang, Y. Zhang, S. V. Dubonos, et al., "Electric field effect in atomically thin carbon films," Science, vol. 306, no. 5696, pp. 666-669, Oct. 2004.
[11] Y. Banadaki, K. Mohsin, and A. Srivastava, "A graphene field effect transistor for high temperature sensing applications," in Proc. SPICE (Smart Structures/NDE: Nano-, Bio-, and Info-Tech Sensors and System: SSNO6), vol. 9060, 7 pp, 16-16 Apr. 2014.
[12] S. P. Mohanty, Nanoelectronic Mixed-Signal System Design, McGraw-Hill Education New York, 2015.
[13] S. Morozov, et al., "Giant intrinsic carrier mobilities in graphene and its bilayer," Physical Review Letters, vol. 100, no. 1, Article ID 016602, 16 Jan. 2008.
[14] A. K. Geim and K. S. Novoselov, "The rise of graphene," Nature Materials, vol. 6, no. 3, pp. 183-191, Mar. 2007.
[15] K. S. Novoselov, D. Jiang, F. Schedin, T. Booth, V. Khotkevich, S. Morozov, et al., "Two-dimensional atomic crystals," in Proc. of the National Academy of Sciences, vol. 102, no. 30, pp. 10451-10453, Jul. 2005.
[16] X. Du, I. Skachko, A. Barker, and E. Y. Andrei, "Approaching ballistic transport in suspended graphene," Nature Nanotechnology, vol. 3, no. 8, pp. 491-495, Aug. 2008.
[17] S. Joshi and U. Alabawi, "Comparative analysis of 6T, 7T, 8T, 9T, and 10T realistic CNTFET based SRAM," J. of Nanotechnology, vol. 2017, no. 5, pp. 1-9, May 2017.
[18] J. S. Moon and D. K. Gaskill, "Graphene: its fundamentals to future applications," IEEE Trans. on Microwave Theory and Techniques, vol. 59, no. 10, pp. 2702-2708, Oct. 2011.
[19] E. Kougianos, S. Joshi, and S. P. Mohanty, "Multi-swarm optimization of a graphene FET based voltage controlled oscillator circuit," in Proc. IEEE Computer Society Annual Symp. on VLSI, ISVLSI’15, pp. 567-572, Montpellier, France, 8-10 Jul. 2015.
[20] M. Gholipour, Y. Y. Chen, A. Sangai, N. Masoumi, and D. Chen, "Analytical SPICE-compatible model of Schottky-barrier-type GNRFETs with performance analysis," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 2, pp. 650-663, Mar. 2015.
[21] Y. Y. Chen, A. Sangai, M. Gholipour, and D. Chen, "Graphene nano-ribbon field-effect transistors as future low-power devices," in Proc. Int. Symp. on Low Power Electronics and Design, ISLPED’13, pp. 151-156, Beijing, China, 4- 5 Sept. 2013.
[22] M. Choudhury, Y. Yoon, J. Guo, and K. Mohanram, "Technology exploration for graphene nanoribbon FETs," in Proc. 45th ACM/IEE Design Automation Conf., pp. 272-277, Anaheim, CA, USA, 8-13 Jun. 2008.
[23] S. Joshi, S. P. Mohanty, E. Kougianos, and V. P. Yanambaka, "Graphene nanoribbon field effect transistor based ultra-low energy SRAM design," in Proc. IEEE Int. Symp. on Nanoelectronic and Information Systems, pp. 76-79, Gwalior, India, 19-21 Dec. 2016.
[24] Y. Y. Chen, A. Sangai, A. Rogachev, M. Gholipour, G. Iannaccone, G. Fiori, et al., "A SPICE-compatible model of MOS-type graphene nano-ribbon field-effect transistors enabling gate-and circuit-level delay and power analysis under process variation," IEEE Trans. on Nanotechnology, vol. 14, no. 6, pp. 1068-1082, Nov. 2015.
[25] Y. Y. Chen, et al., "A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation," in Proc. Design, Automation & Test in Europe Conf. & Exhibition, pp. 1789-1794, Grenoble, France, 18-23 Mar. 2013.
[26] A. Rogachev, Evaluating the Effect of Process Variation on Silicon and Graphene Nano-Ribbon Based Circuits, M.Sc. Thesis, University of Illinios-Urbana-Champaig, 2012.
[27] M. Mishra, R. S. Singh, and A. Imran, "Performance optimization of GNRFET Inverter at 32 nm technology node," in Materials Today: Proc., vol. 4, no. 9, pp. 10607-10611, Oct. 2017.
[28] Y. Yoon, G. Fiori, S. Hong, G. Iannaccone, and J. Guo, "Performance comparison of graphene nanoribbon FETs with Schottky contacts and doped reservoirs," IEEE Trans. on Electron Devices, vol. 55, no. 9, pp. 2314-2323, Aug. 2008.
[29] D. G. Anil, Y. Bai, and Y. Choi, "Performance evaluation of ternary computation in SRAM design using graphene nanoribbon field effect transistors," in Proc. IEEE 8th Annual Computing and Communication Workshop and Conf., pp. 382-388, Las Vegas, NV, USA, 8-10 Jan. 2018.
[30] M. Gholipour, Y. Y. Chen, A. Sangai, and D. Chen, "Highly accurate SPICE-compatible modeling for single-and double-gate GNRFETs with studies on technology scaling," in Proc. of the Conf. on Design, Automation & Test in Europe, 6 pp., Dresden, Germany, 24-28 Mar. 2014.
[31] M. W. Phyu, Low-Voltage Low-Power CMOS Flip-Flops, Ph.D. Thesis, Nanyang Technological University, 2009.
[32] N. H. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th Edition, Addison-Wesley, 2010.
[33] N. Nedovic, W. W. Walker, and V. G. Oklobdzija, "A test circuit for measurement of clocked storage element characteristics," IEEE J. of Solid-State Circuits, vol. 39, no. 8, pp. 1294-1304, Aug. 2004.
[34] V. G. Oklobdzija, V. M. Stojanovic, D. M. Markovic, and N. M. Nedovic, Digital System Clocking: High-Performance and Low-Power Aspects, John Wiley & Sons, 2005.
[35] D. M. Harris, "Sequential element timing parameter definition considering clock uncertainty," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 11, pp. 2705-2708, Nov. 2014.
[36] A. Islam and M. Hasan, "A technique to mitigate impact of process, volatge and temperature variations on design metrcis of SRAM cell," Microelectronics Reliability, vol. 52, no. 2, pp. 405-411, Feb. 2012.
