Statistical Analysis and Modeling of CMRR and PSRR Random Variations in a Nano-CMOS Transconductance Amplifier
Subject Areas : electrical and computer engineering
1 -
2 -
Abstract :
With advancement of integrated circuit technology and aggressive scaling into nanometer regime, statistical variability in device electrical characteristics caused by discreteness of charge and fabrication process variations has significantly increased. These variations in turn result in fluctuations in output characteristics of important analog building blocks and in particular, amplifiers. In this paper, with the aid of Monte-Carlo simulations for a transconductance amplifier and using 1000 different compact models of MOSFET transistors in 35nm technology node, statistical variations of important circuit parameters are investigated and analyzed based on their statistical distributions. Moreover, statistical correlations between circuit parameters are extracted. Analysis of statistical variations for circuit parameters and their correlations has a direct impact on reduction of cost and time of a design and thus, is of great amount of significance.
[1] E. Bazizi, et al., "Impact of backplane configuration on the statistical variability in 22 nm FDSOI CMOS," in Proc. Int. Conf. on Simulation of Semiconductor Processes and Devices, SISPAD'15, pp. 345-348, Washington, DC, USA, 9-11 Sept. 2015.
[2] S. S. Sylvia, et al., "Effect of random, discrete source dopant distributions on nanowire tunnel FETs," IEEE Trans. on Electron Devices, vol. 61, no. 6, pp. 2208-2214, Jun. 2014.
[3] K. Nayak, et al., "Metal-gate granularity-induced threshold voltage variability and mismatch in Si gate-all-around nanowire n-MOSFETs," IEEE Trans. on Electron Devices, vol. 61, no. 11, pp. 3892-3895, Nov. 2014.
[4] X. Wang, et al., "Interplay between process-induced and statistical variability in 14 nm CMOS technology double-gate SOI FinFETs," IEEE Trans. on Electron Devices, vol. 60, no. 8, pp. 2485-2492, Aug. 2013.
[5] L. L. Lewyn, T. Ytterdal, C. Wulff, and K. Martin, "Analog circuit design in nanoscale CMOS technologies," Proceedings of the IEEE, vol. 97, no. 10, pp. 1687-1714, Oct. 2009.
[6] X. Li, B. Taylor, Y. Chien, and L. T. Pileggi, "Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization," in Proc. IEEE/ACM Int. Conf. on Computer-Aided Design, ICCAD'07, pp. 450-457, San Jose, CA, USA, 4-8 Nov. 2007.
[7] C. C. Enz and G. C. Temes, "Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization," Proceedings of the IEEE, vol. 84, no. 11, pp. 1584-1614, Nov. 1996.
[8] C. G. Yu and R. L. Geiger, "Nonideality consideration for high-precision amplifiers-analysis of random common-mode rejection ratio," IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, vol. 40, no. 1, pp. 1-12, Jan. 1993.
[9] P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, John Wiley & Sons, Inc., 2001.
[10] R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for Signal Processing, New York, Wiley-Interscience, p. 614, vol. 1, 1986.
[11] J. Brown, "Differential amplifiers that reject common-mode currents," IEEE J. Solid-State Circuits, vol. 6, no. 6, pp. 385-391, Dec. 1971.
[12] P. VanPeteghem and J. Duque-Carrillo, "A general description of common-mode feedback in fully-differential amplifiers," in Proc. IEEE Int. Symp. on Circuits and Systems, vol. 4, pp. 312-320, New Orleans, LA, USA, 1-3 May 1990.
[13] G. Meyer-Brotz and A. Kley, "The common-mode rejection of transistor differential amplifiers," IEEE Trans. on Circuit Theory, vol. 13, no. 2, pp. 171-175, Jun. 1966.
[14] M. J. Pelgrom, A. C. Duinmaijer, and A. P. Welbers, "Matching properties of MOS transistors," IEEE J. of Solid-State Circuits, vol. 24, no. 5, pp. 1433-1439, Oct. 1989.
[15] J. P. M. Brito and S. Bampi, "A DC offset and CMRR analysis in a CMOS 0.35 μm operational transconductance amplifier using Pelgrom's area/accuracy tradeoff," Microelectronics J., vol. 40, no. 9, pp. 1281-1292, Sept. 2009.
[16] B. Cheng, et al. "Statistical variability compact modelling strategy for BSIM4 and PSP," IEEE Design and Test of Computers, vol. 27, no. 2, pp. 26-35, Mar./Apr. 2010.
[17] S. K. Saha, "Modelling process variability in scaled CMOS technology," IEEE Design and Test of Computers, vol. 27, no. 2, pp. 8-16, Mar./Apr. 2010.
[18] A. Asenov, et al., "Simulation of statistical variability in nano-CMOS transistors using drift-diffusion, Monte Carlo and non-equilibrium Green's function technique," J. of Comp. Electronics, vol. 8, no. 3-4, pp. 349-373, Oct. 2009.
