List of Articles low power

• Open Access Article
  • Abstract Page
  • Full-Text
  
  1 - Design and Implementation of an Ultra-Wide Band, High Precision, and Low Noise Frequency Synthesizer
  Yas Hosseini Tehrani Nasser Masoumi
  10.7508/jist.2017.20.001
  This paper presents system-level design and implementation of an ultra-wide tunable, high precision, fast locking, low phase noise, and low power portable fractional-N frequency synthesizer. The output frequency of the proposed design is ranged from 54 MHz to 6.8GHz. Th More

  This paper presents system-level design and implementation of an ultra-wide tunable, high precision, fast locking, low phase noise, and low power portable fractional-N frequency synthesizer. The output frequency of the proposed design is ranged from 54 MHz to 6.8GHz. The VCO cores cover frequencies from 3.4GHz to 6.8GHz. The programmable output dividers allow generation of the lower frequencies. The frequency resolution of the implemented system is ±20 parts per million (ppm) over -40/85ºC. The output power is tunable between -4dBm and +5dBm. The implemented system has a phase adjust feature that allows shifting of the output phase in relation to the reference oscillator ranged from 0° to 180°. It can generate a wide range, high precision, and linear frequency sweep. The sweep rate, frequency step, and frequency range are tunable. The new frequency tuning algorithm, named Yas algorithm, is proposed to improve frequency precision of the synthesizer. To demonstrate the efficiency of the Yas algorithm, the simulation result MATLAB and the experimental measurements are presented. The system consumes 300mA; therefore, it can be powered by Li-Ion battery. The output phase noise is -95.55 dBc/Hz at 1KHz offset from 3GHz. The experimental measurement results demonstrate that the implemented frequency synthesizer can be used for applications, such as oscillator of spectrum analyzer, automatic test equipment, FMCW radars, high-performance clock source for high speed data converter Manuscript profile
• Open Access Article
  • Abstract Page
  • Full-Text
  
  2 - Design and ُSimulation of a New High CMRR, High Bandwidth and Low Power Current Mode Instrumentation Amplifier Based on FDCCII
  S.  Ahmadi S. J. Azhari
  In this paper a novel topology of CMIA based on FDCCII is proposed. Due to benefiting from current mode signal processing, unlike the most of the previously reported IAs, the proposed FDCCII based structure doesn't need well-matched resistors or active blocks to obtain More

  In this paper a novel topology of CMIA based on FDCCII is proposed. Due to benefiting from current mode signal processing, unlike the most of the previously reported IAs, the proposed FDCCII based structure doesn't need well-matched resistors or active blocks to obtain high CMRR and inherently can improve CMRR, bandwidth, power consumption and it has better frequency performances. On the other side, unlike other current mode types of this group, using fully differential structure decreases the mismatch effect in electronic blocks. Both of these advantages significantly reduced the structure size and power consumption while improving bandwidth and CMRR and makes it an excellent and an unbeatable choice for integration. In the proposed circuit, CMRR as the most important property of IA has been greatly improved by using a current subtracting stage. The CMIA has been designed using 0.18 um CMOS Technology under ±1 V supply voltages and the performance of the CMIA has been verified using HSPICE software in transistor level. The CMIA has achieved voltage CMRR of 227.4 dB, voltage CMRR bandwidth of 8.98 KHz, differential voltage gain bandwidth of 9.08 MHz and output offset voltage of 2.23 uV and the IA’s power dissipation is only 348 uW Manuscript profile
• Open Access Article
  • Abstract Page
  • Full-Text
  
  3 - Design of a Fully Integrated Low Voltage, High Efficiency Capacitive, DC-DC Converter for Energy Harvesting Applications
  A. Hassanzadeh F. Alirezaei
  In this paper, a low voltage boost DC-DC converter has been presented. The circuit can be used for increasing the output voltage of miniature low voltage generators such as TEG, solar and piezoelectric. The converter is fully integrated and works with low voltages as lo More

  In this paper, a low voltage boost DC-DC converter has been presented. The circuit can be used for increasing the output voltage of miniature low voltage generators such as TEG, solar and piezoelectric. The converter is fully integrated and works with low voltages as low as 200 mV, and the output voltage can reach 1 V. Body biasing has been used to handle low input voltages. The output power density is 50 µW/mm2, and the converter uses 5 cross coupled stages with 76% efficiency. The maximum total efficiency of the converter for 6 µA load is 52%. The converter uses 0.2 mm2 of chip area using 90 nm technology. Manuscript profile
• Open Access Article
  • Abstract Page
  • Full-Text
  
  4 - Design and Simulation of a Low Power and High-Speed CMOS Double-Tail Comparator
  Akbar Heidaritabar habib Adarang seyed saleh Ghoreishi Reza Yousefi
  The need for low power and high-speed ADC pushes for dynamic comparators to reduce power consumption and maximize speed. This paper presents an analysis of delay, speed, and comparator considerations, and analytical expressions are derived. Using the equation expression More

  The need for low power and high-speed ADC pushes for dynamic comparators to reduce power consumption and maximize speed. This paper presents an analysis of delay, speed, and comparator considerations, and analytical expressions are derived. Using the equation expressions, we can understand the design of comparators and make trade-offs. Based on the presented analysis, a new dynamic comparator is proposed by modifying the circuit of the conventional tail comparator for high speed and low power at small supply voltages without complicating the circuit design, resulting in a remarkable reduction in delay time and incremental speed. Simulation results in a 180 nm CMOS technology confirm the analysis results. It is shown that the proposed conventional tail comparator reduces power consumption and increases speed. The simulation results show that the proposed comparator operates up to 2.5GHz with a delay of 69ps and consumes only 329 μW at a supply voltage of 1.2 V and an offset standard deviation of 7.8 mW. Manuscript profile
• Open Access Article
  • Abstract Page
  • Full-Text
  
  5 - LSBB Voltage Level Shifter based on Body Biasing
  Reza Darvish khalilabadi amir bavafa toosi
  Designers of modern digital and analog systems have been using multiple voltage levels in one circuit to increase performance. To convert voltage levels in high-performance circuits, it is necessary to use voltage level shifter (LS) circuits with high speed and low powe More

  Designers of modern digital and analog systems have been using multiple voltage levels in one circuit to increase performance. To convert voltage levels in high-performance circuits, it is necessary to use voltage level shifter (LS) circuits with high speed and low power consumption. In this article, a high-performance LS circuit called LSBB (Level Shifter based on Body Biasing) is presented. LSBB consists of three parts: body biasing, current mirror circuit, and pull-up and pull-down circuit. The main idea of this design is to use the biasing circuit to depend on the base of the body of the transistors of the input stages to the VDDL voltage. This dependence leads to changes in the threshold voltage and as a result changes in the delay and power consumption to increase the performance of the circuit. Implementation in 180 nm TSMC technology and simulation with VDDL equal to 0.4 V, VDDH equal to 1.8 V and input frequency 1 MHz indicates the correct operation and high-performance of the proposed circuit, the delay values are 21.9 nS, the power consumption is 129 nW and the PDP equal to 2825 nW*nS confirms the high-performance of LSBB. Manuscript profile