Design and Simulation of a Low Power and High-Speed CMOS Double-Tail Comparator
Subject Areas : electrical and computer engineeringAkbar Heidaritabar 1 , habib Adarang 2 , seyed saleh Ghoreishi 3 , Reza Yousefi 4
1 - Department of Electrical Engineering,Islamic Azad University, Nour Branch
2 -
3 - Islamic Azad University, Nour Branch
4 - Islamic Azad University, Nour Branch
Keywords: CMOS design, high-speed, low power, double-tail comparator,
Abstract :
The need for low power and high-speed ADC pushes for dynamic comparators to reduce power consumption and maximize speed. This paper presents an analysis of delay, speed, and comparator considerations, and analytical expressions are derived. Using the equation expressions, we can understand the design of comparators and make trade-offs. Based on the presented analysis, a new dynamic comparator is proposed by modifying the circuit of the conventional tail comparator for high speed and low power at small supply voltages without complicating the circuit design, resulting in a remarkable reduction in delay time and incremental speed. Simulation results in a 180 nm CMOS technology confirm the analysis results. It is shown that the proposed conventional tail comparator reduces power consumption and increases speed. The simulation results show that the proposed comparator operates up to 2.5GHz with a delay of 69ps and consumes only 329 μW at a supply voltage of 1.2 V and an offset standard deviation of 7.8 mW.
[1] H. Ghasemian, R. Ghasemi, E. Abiri, and M. R. Salehi, "A novel high-speed low-power dynamic comparator with complementary differential input in 65 nm CMOS technology," Microelectronics J., vol. 92, Article ID: 104603, 9 pp., Oct. 2019.
[2] A. Mesgarani, M. N. Alam, F. Z. Nelson, and S. U. Ay, "Supply boosting technique for designing very low-voltage mixed-signal circuits in standard CMOS," in Proc. IEEE Int. Midwest Symp. Circuits Syst. Dig. Tech. Papers, pp. 893-896, Seattle, WA, USA, 1-4 Aug. 2010.
[3] M. Maymandi-Nejad and M. Sachdev, "1 bit quantiser with rail to rail input range for sub-1V modulators," IEEE Electron. Lett., vol. 39, no. 12, pp. 894-895, Jan. 2003.
[4] M. T. Mustaffa, "A low power comparator utilizing MTSCStack, DTTS, and bulk-driven techniques," IJRES, vol. 10, no. 3, pp. 221-229, Nov. 2021.
[5] B. Goll and H. Zimmermann, "A 0.12 μm CMOS comparator requiring 0.5 V at 600 MHz and 1.5 V at 6 GHz," in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, pp. 316-317, San Francisco, CA, USA, 11-15 Feb. 2007.
[6] D. Shinkel, E. Mensink, E. Klumperink, E. van Tuijl, and B. Nauta, "A double-tail latch-type voltage sense amplifier with 18 ps setup + hold time," in Proc. IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, pp. 314-315, San Francisco, CA, USA, 11-15 Feb. 2007.
[7] P. Nuzzo, F. D. Bernardinis, P. Terreni, and G. Van der Plas, "Noise analysis of regenerative comparators for reconfigurable ADC architectures," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 6, pp. 1441-1454, Jul. 2008.
[8] B. Goll and H. Zimmermann, "Low-power 600 MHz comparator for 0.5 V supply voltage in 0.12 μm CMOS," IEEE Electron. Lett., vol. 43, no. 7, pp. 388-390, Mar. 2007.
[9] A. Nikoozadeh and B. Murmann, "An analysis of latched comaprator offset due to load capacitor mismatch," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 12, pp. 1398-1402, Dec. 2006.
[10] Y. L. Wong, M. H. Cohen, and P. A. Abshire, "A floating-gate comparator with automatic offset adaptation for 10-bit data conversion," IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 52, no. 7, pp. 1316-1326, Jul. 2005.
[11] S. Babayan-Mashhadi and R. Lotfi, "An offset cancellation technique for comparators using body-voltage trimming," Int. J. Analog Integr. Circuits Signal Process, vol. 73, no. 3, pp. 673-682, Dec. 2012.
[12] V. Jain, "An intensive study of thermal effects in high speed low power CMOS dynamic comparators," in Proc. IEEE Int. Conf. on Communication and Electronics Systems, pp. 343-352, Coimbatre, India, 8-10 Jul. 2021.
[13] L. Nagy, D. Arbet, M. Kov'ac, M. Sovcik, and V. Stopjakov'a, "Performance analysis of ultra low-voltage rail-to-rail comparator in 130 nm CMOS technology," in Proc. IEEE AFRICON, 5 pp., Accra, Ghana, 25-27 Sept. 2019.
[14] S. Wang, C. Ghezzi, C. Camp, and A. Laville, "A 24 MHz relaxation oscillator using single current mode comparator with ±1.67% drift from -40◦C to +175◦C for automotive sensor application," in Proc. 2020 IEEE Sensors, 5 pp., Rotterdam, Netherlands, 25-28 Oct. 2020.
[15] M. Bchir, N. Hassen, and K. Besbes, "A novel high-performance ADC flash based on bulk-driven quasi-floating gate current mirror," in Proc. Int. Multi-Conf. on Systems, Signals & Devices, SSD'20, pp. 780-785, Monastir, Tunisia, 20-23 Jul. 2020.
[16] M. Yavari, N. Maghari, and O. Shoaei, "An accurate analysis of slew rate for two-stage CMOS opamps," IEEE Trans. on Circuits and Systems II, vol. 52, no. 3, pp. 164-167, Mar. 2005.
[17] N. Dupré, Y. Bidaux, O. Dubrulle, and G. F. Close, "A stray-field-immune magnetic displacement sensor with 1% accuracy," IEEE Sensors J., vol. 20, no. 19, pp. 11405-11411, 1 Oct. 2020.
