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Open Access Article
1 - Design of FPGA-based processor for SHA-2 series cryptographic algorithms Design ترجمههای design اسمفراوانی طرح plan, design, layout, project, scheme, plot نقشه map, plan, plot, scheme, plat, chart زمینه background, context, ground, setting, base, terrain تدبیر measure, plan, contraption, gimmick, contrivance, scheme قصد intention, intent, purpose, attempt, will, determination طراح ریزی design خیال imagination, phantom, illusion, thought, fiction, mind فعل طرح کردن design, plan, draft, draw, lay, bring forth قصد کردن attempt, decide, design, meditate تخصیص دادن allot, allocate, apportion, consecrate, give, design تدبیر کردن devise, contrive, meditate, compass, machinate, design تعریفهای design اسم ۱ a plan or drawing produced to show the look and function or workings of a building, garment, or other object before it is built or made. he has just unveiled his design for the new museum مترادفها: planblueprintdrawingscale drawingsketchoutlinemapplotdiagramdelineationdraftdepictionrepresentationartist's impressionschememodelprototypeproposal ۲ an arrangement of lines or shapes created to form a pattern or decoration. pottery with a lovely blue and white design مترادفها: patternmotifdevicestylearrangementcompositionmakeuplayoutconstitutionconfigurationorganizationconstructionshapeformformationfigure purpose, planning, or intention that exists or is thought to exist behind an action, fact, or material object. the appearance of design in the universe مترادفها: intentionaimpurposeplanintentobjectiveobjectgoalendtargetpointhopedesirewishdreamaspirationambitionidea فعل ۱ decide upon the look and functioning of (a building, garment, or other object), by making a detailed drawing of it. a number of architectural students were designing a factory مترادفها: plandraw plans ofdrawsketchoutlinemap outplotblock outdelineatedraftdepictinventoriginatecreatethink upcome up withdeviseformformulateconceivemakeproducedevelopfashionfabricateforgehatchcoindream up مترادف design اسم planpatternintention فعل planinventdream upintend ۹۱ مترادف دیگر
neda sedghahrabi Mohammad Ali Jabraeil JamaliSecure decryption algorithms are a type of cryptographic algorithms whose importance in today's society has been highlighted by applications such as the use of personal digital tools to maintain confidentiality. On the other hand, with the advancement of technology, the MoreSecure decryption algorithms are a type of cryptographic algorithms whose importance in today's society has been highlighted by applications such as the use of personal digital tools to maintain confidentiality. On the other hand, with the advancement of technology, the need to implement these algorithms on flexible platforms can be challenging. Reducing the area and speeding up the execution of operations are the main challenges for designing and implementing these algorithms. This paper proposes a new architecture for the FPGA-based processor for SHA-2 series cryptographic algorithms. In the proposed processor, the use of memory units and multi-port data path, followed by parallel processor performance, has reduced the use of resources and increased the speed of data processing. Processor architecture for SHA-2 cryptographic algorithms is modeled in VHDL and implemented on the FPGA platform in the Virtex series by ISE software. Implementation results show that the proposed compact processor compared to previous tasks with similar objectives, was able to increase the operating frequency for the SHA-256 cryptographic algorithm by 25% and occupy 55% less space for the SHA-512 cryptographic algorithm to the desired level of operational power and efficiency. Also maintain. The proposed processor is suitable for applications such as trusted mobile platforms (TMP), digital currency (Bitcoin) and secure on-chip network routing (NoC). Manuscript profile -
Open Access Article
2 - Low Complexity Median Filter Hardware for Image Impulsive Noise Reduction
Hossein Zamani HosseinAbadi samavi96 samavi96 Nader KarimiMedian filters are commonly used for removal of the impulse noise from images. De-noising is a preliminary step in online processing of images, thus hardware implementation of median filters is of great interest. Hence, many methods, mostly based on sorting the pixels, MoreMedian filters are commonly used for removal of the impulse noise from images. De-noising is a preliminary step in online processing of images, thus hardware implementation of median filters is of great interest. Hence, many methods, mostly based on sorting the pixels, have been developed to implement median filters. Utilizing vast amount of hardware resources and not being fast are the two main disadvantages of these methods. In this paper a method for filtering images is proposed to reduce the needed hardware elements. A modular pipelined median filter unit is first modeled and then the designed module is used in a parallel structure. Since the image is applied in rows and in a parallel manner, the amount of necessary hardware elements is reduced in comparison with other hardware implementation methods. Also, image filtering speed has increased. Implementation results show that the proposed method has advantageous speed and efficiency. Manuscript profile -
Open Access Article
3 - Automated Implementation of Quantum Circuits on QFPGA for Emulation
M. Heidarzadeh Mohammad Danaee FarThis paper defines an optimal architecture for the FPGA using exact methods. In order to achieve this goal, optimal placement and routing solutions are found using the integer linear programming techniques. After redefining the internal architecture of the logic blocks, MoreThis paper defines an optimal architecture for the FPGA using exact methods. In order to achieve this goal, optimal placement and routing solutions are found using the integer linear programming techniques. After redefining the internal architecture of the logic blocks, quantum circuits are partitioned by a heuristic algorithm in order to reach maximum utilization of the resources inside logic blocks and minimum delay of the paths traversed by the q-bits in the circuit. Experimental results show that FPGA architecture modifications can result in the reduction of the delay of critical paths of circuits by up to half in some cases and in a considerable reduction of the number of channels used for routing. Furthermore, the results show that defining the logic blocks with 12 q-bits instead of 4 q-bits can decrease circuits delay and the number of used channels to a large extent. Manuscript profile -
Open Access Article
4 - A High Performance Dual Stage Face Detection Algorithm Implementation using FPGA Chip and DSP Processor
M V Ganeswara Rao P Ravi Kumar T BalajiA dual stage system architecture for face detection based on skin tone detection and Viola and Jones face detection structure is presented in this paper. The proposed architecture able to track down human faces in the image with high accuracy within time constrain. A no MoreA dual stage system architecture for face detection based on skin tone detection and Viola and Jones face detection structure is presented in this paper. The proposed architecture able to track down human faces in the image with high accuracy within time constrain. A non-linear transformation technique is introduced in the first stage to reduce the false alarms in second stage. Moreover, in the second stage pipe line technique is used to improve overall throughput of the system. The proposed system design is based on Xil¬inx’s Virtex FPGA chip and Texas Instruments DSP processor. The dual port BRAM memory in FPGA chip and EMIF (External Memory Interface) of DSP processor are used as interface between FPGA and DSP processor. The proposed system exploits advantages of both the computational elements (FPGA and DSP) and the system level pipelining to achieve real time perform¬ance. The present system implementation focuses on high accurate and high speed face detec¬tion and this system evaluated using standard BAO image database, which include images with different poses, orientations, occlusions and illumination. The proposed system attained 16.53 FPS frame rate for the input image spatial resolution of 640X480, which is 23.4 times faster detection of faces compared to MATLAB implementation and 12.14 times faster than DSP implementation and 2.1 times faster than FPGA implementation. Manuscript profile