List of Articles Optimization Algorithms

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  1 - Reducing Energy Consumption in Sensor-Based Internet of Things Networks Based on Multi-Objective Optimization Algorithms
  Mohammad sedighimanesh Hessam  Zandhessami Mahmood  Alborzi Mohammadsadegh  Khayyatian
  10.52547/jist.15639.10.39.180
  Energy is an important parameter in establishing various communications types in the sensor-based IoT. Sensors usually possess low-energy and non-rechargeable batteries since these sensors are often applied in places and applications that cannot be recharged. The mos More

  Energy is an important parameter in establishing various communications types in the sensor-based IoT. Sensors usually possess low-energy and non-rechargeable batteries since these sensors are often applied in places and applications that cannot be recharged. The most important objective of the present study is to minimize the energy consumption of sensors and increase the IoT network's lifetime by applying multi-objective optimization algorithms when selecting cluster heads and routing between cluster heads for transferring data to the base station. In the present article, after distributing the sensor nodes in the network, the type-2 fuzzy algorithm has been employed to select the cluster heads and also the genetic algorithm has been used to create a tree between the cluster heads and base station. After selecting the cluster heads, the normal nodes become cluster members and send their data to the cluster head. After collecting and aggregating the data by the cluster heads, the data is transferred to the base station from the path specified by the genetic algorithm. The proposed algorithm was implemented with MATLAB simulator and compared with LEACH, MB-CBCCP, and DCABGA protocols, the simulation results indicate the better performance of the proposed algorithm in different environments compared to the mentioned protocols. Due to the limited energy in the sensor-based IoT and the fact that they cannot be recharged in most applications, the use of multi-objective optimization algorithms in the design and implementation of routing and clustering algorithms has a significant impact on the increase in the lifetime of these networks. Manuscript profile
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  2 - ARASP: An ASIP Processor for Automated Reversible Logic Synthesis
  Zeinab Kalantari Marzieh Gerami Mohammad eshghi
  10.52547/jist.16264.10.40.279
  Reversible logic has been emerged as a promising computing paradigm to design low power circuits in recent years. The synthesis of reversible circuits is very different from that of non-reversible circuits. Many researchers are studying methods for synthesizing reversib More

  Reversible logic has been emerged as a promising computing paradigm to design low power circuits in recent years. The synthesis of reversible circuits is very different from that of non-reversible circuits. Many researchers are studying methods for synthesizing reversible combinational logic. Some automated reversible logic synthesis methods use optimization algorithms Optimization algorithms are used in some automated reversible logic synthesis techniques. In these methods, the process of finding a circuit for a given function is a very time-consuming task, so it’s better to design a processor which speeds up the process of synthesis. Application specific instruction set processors (ASIP) can benefit the advantages of both custom ASIC chips and general DSP chips. In this paper, a new architecture for automatic reversible logic synthesis based on an Application Specific Instruction set Processors is presented. The essential purpose of the design was to provide the programmability with the specific necessary instructions for automated synthesis reversible. Our proposed processor that we referred to as ARASP is a 16-bit processor with a total of 47 instructions, which some specific instruction has been set for automated synthesis reversible circuits. ARASP is specialized for automated synthesis of reversible circuits using Genetic optimization algorithms. All major components of the design are comprehensively discussed within the processor core. The set of instructions is provided in the Register Transform Language completely. Afterward, the VHDL code is used to test the proposed architecture. Manuscript profile