ARASP: An ASIP Processor for Automated Reversible Logic Synthesis
Subject Areas : IT Strategy
Zeinab Kalantari
1
,
Marzieh Gerami
2
,
Mohammad eshghi
3
1 - Department of Computer Engineering, Rafsanjan Branch, Islamic Azad University, Rafsanjan, Iran
2 - Department of Computer Engineering, Shahrekord Branch, Islamic Azad University, Shahrekord, Iran
3 - Faculty of Electrical and Computer Engineering, Shahid Beheshti University, Tehran, Iran
Keywords: Reversible logic, Optimization Algorithms, Application Specific Instruction Set Processors, ASIP, RTL.,
Abstract :
Reversible logic has been emerged as a promising computing paradigm to design low power circuits in recent years. The synthesis of reversible circuits is very different from that of non-reversible circuits. Many researchers are studying methods for synthesizing reversible combinational logic. Some automated reversible logic synthesis methods use optimization algorithms Optimization algorithms are used in some automated reversible logic synthesis techniques. In these methods, the process of finding a circuit for a given function is a very time-consuming task, so it’s better to design a processor which speeds up the process of synthesis. Application specific instruction set processors (ASIP) can benefit the advantages of both custom ASIC chips and general DSP chips. In this paper, a new architecture for automatic reversible logic synthesis based on an Application Specific Instruction set Processors is presented. The essential purpose of the design was to provide the programmability with the specific necessary instructions for automated synthesis reversible. Our proposed processor that we referred to as ARASP is a 16-bit processor with a total of 47 instructions, which some specific instruction has been set for automated synthesis reversible circuits. ARASP is specialized for automated synthesis of reversible circuits using Genetic optimization algorithms. All major components of the design are comprehensively discussed within the processor core. The set of instructions is provided in the Register Transform Language completely. Afterward, the VHDL code is used to test the proposed architecture.
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