Nonlinear Analysis of Jitter Transfer in Charge Pump Phase-Locked loops regarding Channel Length Modulation Effect
Subject Areas : electrical and computer engineeringH. Dehbovid 1 , H. Adarang 2 , M. B. Tavakoli 3
1 -
2 - دانشگاه آزاد اسلامی واحد نور
3 -
Abstract :
Due to the nonlinear behavior caused by the charge pump, charge pump phase-locked loops (CPPLLs) are nonlinear systems. In an ideal charge pump, the applied current is constant; however, in practice, it is not constant due to the transistor's non-ideal effects. In this paper, regarding the transistor's channel length modulation effect (CLM) on charge pump’s current, the non-linear differential equation of the system is obtained and shows that the phase lock loop is a nonlinear system with memory and Voltaire Series expansion can be used to analyze it. As a result, a method for estimating a jitter transfer with a second-order filter is proposed. System level simulation is used to validate the analytical results with particular emphasis on the jitter transfer characteristics. The effect of different loop parameters has also been studied. The experiments all show excellent conformance between analytical equations and simulation results.
[1] N. Da Dalt, "Markov chains-based derivation of the phase detector gain in bang-bang PLLs," IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 53, no. 11, pp. 1195-1199, Nov. 2006.
[2] B. Chun and M. P. Kennedy, "Statistical properties of first-order bang-bang PLL with nonzero loop delay," IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 55, no. 10, pp. 1016-1020, Oct. 2008.
[3] S. Tertinek, J. P. Gleeson, and O. Feely, "Statistical analysis of first-order bang-bang phase-locked loops using sign-dependent random walk theory," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 9, pp. 2367-2380, Sep. 2010.
[4] A. Ebrahimi, H. Miar Naimi, and H. Adrang, "Remarks on transient amplitude analysis of MOS cross-coupled oscillators," IEICE Trans. Electron, -C, vol. 94, no. 2, pp. 231-239, 2011.
[5] A. Carlosena and A. M. Lazaro, "Design of high-order phase lock loops," IEEE Trans. on Circuits and Systems-II, Express Briefs, vol. 54, no. 1, pp. 9-13, Jan. 2007.
[6] A. Carlosena, M. Ugarte, and A. J. Lopez-Martin, "Loop filter approximation for PLLs," in Proc. 51st Midwest Symp. on Circuits and Systems, MWSCAS'08, pp. 21-24, Knoxville, TN, USA, 10-13 Aug. 2008.
[7] R. Nonis, N. Da Dalt, P. Palestri, and L. Selmi, "Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture," IEEE J. on Solid-State Circuits, vol. 40, no. 6, pp. 1303-1309, Jun. 2005.
[8] H. Adrang and H. Miar-Naimi, "Modeling of jitter in bang-bang CDR with fourier series analysis," IEEE Trans. on Circuits and Systems-I: Regular Papers, vol. 60, no. 1, pp. 3-10, Jan. 2013.
[9] M. Gholami and G. Ardeshir, "Jitter of delay-locked loops due to PFD," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 10, pp. 2176-2180, Oct. 2014.
[10] P. Paliwal, M. Sattineni, and S. Gupta, "Tradeoffs between settling time and jitter in phase locked loops," IEEE 56th Int.Midwest Symp. on Circuits and Systems, MWSCAS’13, pp. 746-749, Columbus, OH, USA, 4-7 Aug. 2013.
[11] L. D. Tommasi, D. Gorissen, J. Croon, and T. Dhaene, "Surrogate modeling of RF circuit blocks," In: Fitt A., Norbury J., Ockendon H., Wilson E. (eds), Progress in Industrial Mathematics at ECMI 2008. Mathematics in Industry, vol 15. Springer, Berlin, Heidelberg.
[12] L. D. Tommasi, D. Gorissen, J. Croon, and T. Dhaene, "Surrogate modeling of low noise amplifiers based on transistor level simulations," In: Roos J., Costa L. (eds), Scientific Computing in Electrical Engineering SCEE 2008. Mathematics in Industry, vol 14. Springer, Berlin, Heidelberg.
[13] J. C. Nunez-Perez, et al., "Flexible test bed for the behavioural modelling of power amplifiers," The International J. for Computation and Mathematics in Electrical and Electronic Engineering, vol. 33, no. 1-2, pp. 355-375, Jan. 2013.
[14] M. Mollaalipour and H. Miar Naimi, "Volterra series analysis of down-conversion CMOS mixer with high IIP2 and IIP3," in Proc. Int. Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD’12, pp. 201-204, Seville, Spain, 19-21 Sept. 2012.
[15] J. M. Nichols, "Frequency distortion of second- and third-order phase-locked loop systems using a volterra-series approximation," IEEE Trans. on Circuits and Systems-I: Regular Papers, vol. 56, no. 2, pp. 453-459, Feb. 2009.
[16] K. Worden and G. R. Tomlinson, Nonlinearity in Structural Dynamics, Bristol, U.K.: Inst. Phys. Publ., 2001.
[17] P. Wambacq and W. Sansen, Distortion Analysis of Analog Integrated Circuits, Dordrecht, Tthe Netherlands: Kluwer, 1998.
