طراحی فلیپ‌فلاپ‌های جدید سه‌سطحی در نانوالکترونیک با استفاده از CNFET
الموضوعات :
کتایون رهبری
1
(انشکده مهندسی کامپیوتر و برق، دانشگاه آزاد اسلامی واحد یادگار امام خمینی)
سیدعلی حسینی
2
(دانشكده مهندسي كامپيوتر و برق، دانشگاه آزاد اسلامی واحد یادگار امام خمینی)
الکلمات المفتاحية: فلیپ‌فلاپ, مدارات سه‌سطحی, ترانزیستور نانوکربنی,
ملخص المقالة :
استفاده از مدارات چندسطحی می‌تواند باعث کاهش اتصالات داخل تراشه شود. کاهش اتصالات داخل تراشه‌ها باعث کاهش حجم تراشه و اتلاف توان در اتصالات می‌گردد. در سال‌های اخیر با توجه به توانایی نانوالکترونیک در طراحی مدارات چندسطحی، تحقیقاتی در این زمینه رونق گرفته است. مدارات ترتیبی، فلیپ‌فلاپ‌ها از اجزای مهم پردازنده‌ها و مدارات VLSI هستند. در این مقاله برای اولین بار، فلیپ‌فلاپ سه‌سطحی با پالس ژنراتور پیشنهاد گردیده و همین طور فلیپ‌فلاپ دیکد باینری به سه‌سطحی و نیز اولین فلیپ‌فلاپ با استفاده از بافر معرفی شده و سپس این فلیپ‌فلاپ‌ها با خودشان و مدارات قبلی مقایسه شده‌اند. همچنین از این فلیپ‌فلاپ‌ها در طراحی شمارنده سه‌سطحی استفاده شده است. نتایج شبیه‌سازی با نرم‌افزار HSPICE بیانگر عملکرد صحیح مدارات پیشنهادی می‌باشد. در مدل فلیپ‌فلاپ پالس ژنراتور STI %20، در فلیپ‌فلاپ SP %30 و در فلیپ‌فلاپ با بافر 30% بهبود در تأخیر و کاهش در تعداد ترانزیستور وجود دارد. همین طور در جدول مقایسه، مزایا و معایب هر کدام مورد بررسی قرار گرفته است.
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