طراحي و تحلیل مبدل آنالوگ به ديجيتال کمتوان با استفاده از ترانزيستور نانولوله کربني
محورهای موضوعی : مهندسی برق و کامپیوترسعیده حیدری 1 , داریوش دیدبان 2
1 - دانشگاه کاشان
2 - دانشگاه کاشان
کلید واژه: مبدل آنالوگ به ديجيتال, مبدل فلش, مقايسه کننده TIQ, توان مصرفی پایین, انکدر ROM, انکدر Fat tree .,
چکیده مقاله :
امروزه مبدلهاي آنالوگ به ديجيتال به عنوان جزء جداييناپذير از سيستمهاي بر روي تراشه به شمار ميآيند زيرا فاصله بين دنياي فيزيکي آنالوگ و دنياي منطقي ديجيتال را از بين ميبرند. اين امر و تمايل روزافزون به استفاده از تجهيزات قابل حمل، سبب شده ملزومات طراحي اين مبدلها مانند سرعت، توان مصرفي و سطح اشغالي بهبود يابند. راهکارها و روشهاي مختلفي جهت بهبود عملکرد مبدلها ارائه شده که روز به روز در حال پيشرفت ميباشند. با توجه به اهميت روزافزون مبدلها، در اين مقاله يک ADC سريع و کمتوان با استفاده از CNTFET طراحي شده و عملکرد آن با نمونه مشابه MOSFET با همان طول کانال مورد بررسي قرار گرفته و همچنين عملکرد مبدل طراحيشده با دو نوع کدگذار مختلف، ROM و Fat tree مورد مطالعه قرار گرفته است. در ادامه، نتايج شبيهسازي که با بهرهگيري از نرمافزار HSPICE در تغذیه 9/0 ولت به دست آمده ارائه گرديده است. نتايج شبيهسازي مبدل در فناوری CNTFET بهبود قابل توجهي در پارامترهاي توان و تأخير نسبت به طراحي مشابه در فناوری CMOS نشان ميدهد. توان مصرفي و تأخير مبدل مبتنی بر نانولوله کربنی با کدگذار نوع ROM به ترتيب 5/92% و 54% و با کدگذار Fat tree به ترتيب 93% و 72% نسبت به مبدلهای مبتنی بر ترانزیستورهای CMOS بهبود يافتهاند.
Nowadays, analog to digital (A/D) converters are indistinguishable parts of system on chip (soC) structures because they omit the distance between analog real data and digital logic world. Due to this fact and ever increasing trend for using portable instruments, the figures of merit for design of these converters such as speed, power and occupied area are improved. Different methods are proposed to improve the performance of these converters. In this paper, we design a fast and low power ADC using carbon nano-tube field effect transistor (CNTFET) and then its performance is comprehensively compared with a MOSFET based counterpart at the same technology node. The performance is studied two encoders: ROM and Fat tree. The obtained results are presented using HSPICE simulator at 0.9 V power supply. The simulated data from CNTFET based converter shows significant improvements in delay and power compared with its CMOS based counterpart. The power and delay obtained from CNTFET based converter using ROM encoder are improved by 92.5% and 54% with respect to the same parameters obtained from CMOS based design while the improvements using a Fat tree encoder in CNTFET converter reaches 93% and 72% in comparison with CMOS conventional design.
[1] S. Iijima, "Helical microtubules of graphitic carbon," Nature, vol. 354, pp. 56-58, Nov. 1991.
[2] J. W. Wildoer, L. C. Venema, A. G. Rinzler, R. E. Smalley, and C. Dekker, "Electronic structure of atomically resolved carbon nanotubes," Nature, vol. 391, pp. 59-62, Jan. 1998.
[3] Q. Cao and J. A. Rogers, "Ultrathin films of single‐walled carbon nanotubes for electronics and sensors: a review of fundamental and applied aspects," Advanced Materials, vol. 21, no. 1, pp. 29-53, Jan. 2009.
[4] Z. Wu, et al., "Transparent, conductive carbon nanotube films," Science, vol. 305, no. 5688, pp. 1273-1276, Aug. 2004.
[5] J. J. Davis, K. S. Coleman, B. R. Azamian, C. B. Bagshaw, and M. L. Green, "Chemical and biochemical sensing with modified single walled carbon nanotubes," Chemistry-a European J., vol. 9, no. 16, pp. 3732-3739, Aug. 2003.
[6] T. Durkop, S. Getty, E. Cobas, and M. Fuhrer, "Extraordinary mobility in semiconducting carbon nanotubes," Nano Letters, vol. 4, no. 1, pp. 35-39, Jan. 2004.
[7] F. Kreupl, A. P. Graham, G. Duesberg, W. Steinhogl, M. Liebau, E. Unger, et al., "Carbon nanotubes in interconnect applications," Microelectronic Engineering, vol. 64, no. 1-4, pp. 399-408, Oct. 2002.
[8] C. Liu, Y. Fan, M. Liu, H. Cong, H. Cheng, and M. S. Dresselhaus, "Hydrogen storage in single-walled carbon nanotubes at room temperature," Science, vol. 286, 5442, pp. 1127-1129, Nov. 1999.
[9] E. Frackowiak and F. Beguin, "Electrochemical storage of energy in carbon nanotubes and nanostructured carbons," Carbon, vol. 40, no. 10, pp. 1775-1787, Aug. 2002.
[10] S. Park, M. Vosguerichian, and Z. Bao, "A review of fabrication and applications of carbon nanotube film-based flexible electronics," Nanoscale, vol. 5, pp. 1727-1752, 2013.
[11] N. Hamada, S. I. Sawada, and A. Oshiyama, "New one-dimensional conductors: graphitic microtubules," Physical Review Letters, vol. 68, Article No.: 1579, 1992.
[12] R. Marani and A. G. Perri, The Next Generation of FETs: CNTFETs, arXiv preprint arXiv:1511.01356, 2015.
[13] A. Raychowdhury, A. Keshavarzi, J. Kurtin, V. De, and K. Roy, "Carbon nanotube field-effect transistors for high-performance digital circuits-DC analysis and modeling toward optimum transistor structure," IEEE Trans. on Electron Devices, vol. 53, no. 11, pp. 2711-2717, Nov. 20062006.
[14] B. Wei, R. Vajtai, and P. Ajayan, "Reliability and current carrying capacity of carbon nanotubes," Applied Physics Letters, vol. 79, no. 8, pp. 1172-1174, Aug. 2001.
[15] T. Durkop, B. Kim, and M. Fuhrer, "Properties and applications of high-mobility semiconducting nanotubes," J. of Physics: Condensed Matter, vol. 16, no. 18, Article No.: R553, 2004.
[16] M. Zoghi, A. Y. Goharrizi, and M. Saremi, "Band gap tuning of armchair graphene nanoribbons by using antidotes," J. of Electronic Materials, vol. 46, no. 1, pp. 340-346, Jan. 2017.
[17] A. Y. Goharrizi, M. Zoghi, and M. Saremi, "Armchair graphene nanoribbon resonant tunneling diodes using antidote and BN doping," IEEE Trans. on Electron Devices, vol. 63, no. 9, pp. 3761-3768, Jun. 2016.
[18] M. Saremi, M. Saremi, H. Niazi, and A. Y. Goharrizi, "Modeling of lightly doped drain and source graphene nanoribbon field effect transistors," Superlattices and Microstructures, vol. 60, pp. 67-72, Aug. 2013.
[19] S. J. Tans, A. R. Verschueren, and C. Dekker, "Room-temperature transistor based on a single carbon nanotube," Nature, vol. 393, pp. 49-52, 1998.
[20] A. Bachtold, P. Hadley, T. Nakanishi, and C. Dekker, "Logic circuits with carbon nanotube transistors," Science, vol. 294, no. 5545, pp. 1317-1320, 2001.
[21] V. Derycke, R. Martel, J. Appenzeller, and P. Avouris, "Carbon nanotube inter-and intramolecular logic gates," Nano Letters, vol. 1, no. 9, pp. 453-456, 2001.
[22] A. Raychowdhury and K. Roy, "Carbon-nanotube-based voltage-mode multiple-valued logic design," IEEE Trans. on Nanotechnology, vol. 4, no. 2, pp. 168-179, Feb. 2005.
[23] R. Sordan, K. Balasubramanian, M. Burghard, and K. Kern, "Exclusive-OR gate with a single carbon nanotube," Applied Physics Letters, vol. 88, Article No.: 053119, 2006.
[24] A. Hazeghi, T. Krishnamohan, and H. S. P. Wong, "Schottky-barrier carbon nanotube field-effect transistor modeling," IEEE Trans. on Electron Devices, vol. 54, no. 3, pp. 439-445, Mar. 2007.
[25] T. Dang, L. Anghel, and R. Leveugle, "CNTFET basics and simulation," in Proc. Int. Conf. on Design and Test of Integrated Systems in Nanoscale Technology, DTIS’06, pp. 28-33, Tunis, Tunisia, 5-7 Sept.. 2006.
[26] C. Dwyer, M. Cheung, and D. J. Sorin, "Semi-empirical SPICE models for carbon nanotube FET logic," in Proc. 4th IEEE Conf. on Nanotechnology, IEEE-NANO’04, pp. 386-388, Munich, Germany, 16-19 Aug. 2004.
[27] H. Hashempour and F. Lombardi, "An efficient and symbolic model for charge densities in ballistic carbon nanotube FETs," in Proc. IEEE 6th Conf. on Nanotechnology, IEEE-NANO’06, pp. 23-26, Cincinnati, OH, USA, 17-20 Jul. 2006.
[28] B. C. Paul, S. Fujita, M. Okajima, and T. Lee, "Modeling and analysis of circuit performance of ballistic CNFET," in Proc. of the 43rd Annual Design Automation Conf., pp. 717-722, San Francisco, CA, USA., 24-28 Jul. 2006.
[29] P. A. Sankar and G. Sathiyabama, "A novel CNFET technology based 3 bit flash ADC for low-voltage high speed SoC application," International J. of Engineering Research in Africa, vol. 19, pp. 19-36, 2016.
[30] M. H. Moaiyeri, N. Khastoo, M. Nasiri, K. Navi, and N. Bagherzadeh, "An efficient analog-to-digital converter based on carbon nanotube FETs," J. of Low Power Electronics, vol. 12, no. 2, pp. 150-157, 016.
[31] A. Aouaj, A. Bouziane, and A. Nouacry, "Nanotube carbon transistor (CNTFET): IV and CV, a qualitative comparison between fettoy simulator and compact model," in Proc. Int. Conf. on Multimedia Computing and Systems, ICMCS'09, pp. 236-239, Ouarzazate, Morocco, 2-4 Apr. 2009.
[32] J. Deng and H. S. P. Wong, "A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application-part I: model of the intrinsic channel region," IEEE Trans. on Electron Devices, vol. 54, no. 12, pp. 3186-3194, Dec. 2007.
[33] J. Deng and H. S. P. Wong, "A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application-part II: full device model and circuit performance benchmarking," IEEE Trans. on Electron Devices, vol. 54, no. 12, pp. 3195-3205, Dec. 2007.
[34] A. Al-Shaggah, A. Rjoub, and M. Khasawneh, "Carbon nanotube field effect transistor models performance and evaluation," in Proc. IEEE Jordan Conf. on Applied Electrical Engineering and Computing Technologies, AEECT’13, 6 pp., Amman, Jordan, 3-5 Dec. 2013.
[35] G. Cho, F. Lombardi, and Y. B. Kim, "Modelling a CNTFET with undeposited CNT defects," in Proc. IEEE 25th Int. Symp. on Defect and Fault Tolerance in VLSI Systems, DFT’10, pp. 289-296, Kyoto, Japan, 6-8 Oct. 2010.
[36] A. Yukawa, "A CMOS 8-bit high-speed A/D converter IC," IEEE J. of Solid-State Circuits, vol. 20, no. 3, pp. 775-779, Jun?. 1985.
[37] A. G. Dingwall and V. Zazzu, "An 8-MHz CMOS subranging 8-bit A/D converter," IEEE J. of Solid-State Circuits, vol. 20, no. 6, pp. 1138-1143, Dec. 1985.
[38] W. C. Song, H. W. Choi, S. U. Kwak, and B. S. Song, "A 10-b 20-Msample/s low-power CMOS ADC," IEEE J. of Solid-State Circuits, vol. 30, no. 5, pp. 514-521, May 1995.
[39] A. Tangel and K. Choi, "“The CMOS Inverter” as a comparator in ADC designs," Analog Integrated Circuits and Signal Processing, vol. 39, pp. 147-155, 2004.
[40] M. Kulkarni, V. Sridhar, and G. H. Kulkarni, "4-Bit flash analog to digital converter design using CMOS-LTE comparator," in Proc. IEEE Asia Pacific Conf. on Circuits and Systems, APCCAS’10, pp. 772-775, Kuala Lumpur, Malaysia, 6-9 Dec.2 010.
[41] J. Yoo, K. Choi, and A. Tangel, "A 1-GSPS CMOS flash A/D converter for system-on-chip applications," in Proc. IEEE Computer Society Workshop on VLSI, pp. 135-139, Orlando, FL, USA, 19-20 Apr. 2001.
[42] P. A. Bhat and R. N. Mir, "Design of low power high speed 4-bit TIQ based CMOS flash ADC," in Proc. of Int. Conf. on Advances in Computing, pp. 319-328, 2013.
[43] J. Yoo, K. Choi, and D. Lee, "Comparator generation and selection for highly linear CMOS flash analog-to-digital converter," Analog Integrated Circuits and Signal Processing, vol. 35, no. 2, pp. 179-187, May 2003.
[44] D. Lee, J. Yoo, and K. Choi, "Design method and automation of comparator generation for flash A/D converter," in Proc. Int. Symp. on Quality Electronic Design, . pp. 138-142, San Jose, CA, USA, 18-21 Mar. 2002.
[45] A. Islam and M. Hasan, "Dual-diameter variation-immune CNFET-based 7T SRAM cell," Nanosciences and Nanotechnologies: An International J., vol. 1, no. 1, 14 pp., Jul. 2011.
[46] S. Khot, P. Wani, M. Sutaone, and S. Tripathi, "Design of a 45 nm TIQ comparator for high speed and low power 4-Bit flash ADC," International J. on Electrical and Power Engineering, vol. 2, no. 1, pp. 7-10, Feb. 2011.
[47] D. Lee, J. Yoo, K. Choi, and J. Ghaznavi, "Fat tree encoder design for ultra-high speed flash A/D converters," in Proc. 45th Midwest Symp. on Circuits and Systems, . MWSCAS’02, pp. II-II, Tulsa, OK, USA, 4-7 Aug. 2002.
[48] Y. J. Chuang, H. H. Ou, and B. D. Liu, "A novel bubble tolerant thermometer-to-binary encoder for flash A/D converter," in Proc. IEEE Int. Symp. on VLSI Design, Automation and Test, VLSI-TSA-DAT’05, pp. 315-318, Hsinchu, Taiwan, 27-29 Apr. 2005.
[49] D. Ghai, S. P. Mohanty, and E. Kougianos, "A 45 nm flash analog to digital converter for low voltage high speed system on chips," in Proc. of the 13th NASA Symp. on VLSI Design, 10 pp., 2007.
[50] B. Van Hieu, et al., "A new approach to thermometer-to-binary encoder of flash adcs-bubble error detection circuit,", in Proc. IEEE 54th Int. Midwest Symp. on Circuits and Systems, MWSCAS’11, 4 pp., Seoul, South Korea, 7-10 Aug. 2011.
[51] J. Yoo, K. Choi, and J. Ghaznavi, "CMOS flash analog-to-digital converter for high speed and low voltage applications," in Proc. of the 13th ACM Great Lakes Symp. on VLSI, pp. 56-59, Washington, DC, USA, 28-29 Apr. 2003.