طراحی یک تقویت‌کننده ابزاردقیق حالت جریان با CMRR بسیار بزرگ، پهنای باند وسیع، توان مصرفی پایین و ساختاری جدید بر پایه ناقل جریان تمام تفاضلی نسل دوم
محورهای موضوعی : مهندسی برق و کامپیوترسوما احمدی 1 , سیدجواد ازهری 2
1 - دانشگاه علم و صنعت ايران
2 - دانشگاه علم و صنعت ايران
چکیده مقاله :
در این مقاله یک ساختار جدید برای پیاده‌سازی تقویت‌کننده ابزاردقیق حالت جریان (CMIA) بر مبنای ناقل جریان نسل دوم تمام‌تفاضلی (FDCCII) پیشنهاد می‌شود. این ساختار به دلیل بهره‌بردن از امتیازهای کار در حالت جریان بر خلاف تقویت‌کننده‌های ابزاردقیق حالت ولتاژ نیاز به مقاومت‌های همجور برای دست‌یابی به CMRR بزرگ نداشته و به طور ذاتی توانایی بهبود پارامترهای مهم یک CMIA را دارد. همچنین برخلاف سایر انواع جریانی این گروه، استفاده از ساختار تفاضلی تأثیر ناهمجوری بلوک‌های الکترونیکی در عملکرد آن را کاهش داده است. هر دوی این مزیت‌ها اندازه و توان مصرفی ساختار را به شدت کاهش و پهنای باند و CMRR مدار را افزایش داده و این مدار را به نمونه‌ای کم‌نظیر در عملکرد و انتخابی بسیار مناسب برای مجتمع‌سازی تبدیل نموده است. در CMIA طراحی‌شده CMRR به عنوان مهم‌ترین پارامتر یک تقویت‌کننده ابزار دقیق با استفاده از یک طبقه تفاضل‌گیر جریان بهبود داده شده است. طراحی مدار با استفاده از فناوری um 18/0 CMOS تحت ولتاژهای تغذیه V 1± انجام گرفته و عملکرد آن با استفاده از نرم‌افزار HSPICE در سطح ترانزیستور بررسی شده است. نتایج شبیه‌سازی مقادیر CMRR برابر dB 4/227 و پهنای باند KHz 98/8، پهنای باند بهره تفاضلی MHz 08/9، ولتاژ آفست خروجی uV 23/2 و توان مصرفی uW 348 می‌باشد. به عنوان یک امتیاز منحصربه‌فرد، مقدار CMRR در پاسخ مونت‌کارلو (که خطاهای فناوری را نیز منظور می‌نماید) تا dB 68/228 افزایش یافته که به طور نسبی عدم حساسیت ساختار پیشنهادی را به خطاهای فناوری (PVT) به عنوان یک ویژگی بی‌نظیر تأیید می‌نماید.
In this paper a novel topology of CMIA based on FDCCII is proposed. Due to benefiting from current mode signal processing, unlike the most of the previously reported IAs, the proposed FDCCII based structure doesn't need well-matched resistors or active blocks to obtain high CMRR and inherently can improve CMRR, bandwidth, power consumption and it has better frequency performances. On the other side, unlike other current mode types of this group, using fully differential structure decreases the mismatch effect in electronic blocks. Both of these advantages significantly reduced the structure size and power consumption while improving bandwidth and CMRR and makes it an excellent and an unbeatable choice for integration. In the proposed circuit, CMRR as the most important property of IA has been greatly improved by using a current subtracting stage. The CMIA has been designed using 0.18 um CMOS Technology under ±1 V supply voltages and the performance of the CMIA has been verified using HSPICE software in transistor level. The CMIA has achieved voltage CMRR of 227.4 dB, voltage CMRR bandwidth of 8.98 KHz, differential voltage gain bandwidth of 9.08 MHz and output offset voltage of 2.23 uV and the IA’s power dissipation is only 348 uW
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