A Novel Ultra-Broad Band, High Gain, and Low Noise Distributed Amplifier Using Modified Regulated Cascode Configuration (MRGC) Gain-Cell
محورهای موضوعی : Radio frequency and Microwave EngineeringZainab Baharvand 1 , Ahmad Hakimi 2
1 - Graduate University of Advanced Technology
2 - Shahid Bahonar University of Kerman
کلید واژه: Ultra-broad Band , CMOS Distributed Amplifier , Modified Regulated Cascode Configuration (MRGC) , Low Noise,
چکیده مقاله :
In this paper, an ultra-broad bandwidth, low noise, and high gain-flatness CMOS distributed amplifier (CMOS-DA) based on a novel gain-cell is presented. The new gain-cell that enhances the output impedance as a result the gain substantially over conventional RGC is the improved version of Regulated Cascode Configuration (RGC). The new gain-cell based CMOS-DA is analyzed and simulated in the standard 0.13 μm-CMOS technology. The simulated results of the proposed CMOS-DA are included 14.2 dB average power gain with less than ± 0.5 dB fluctuations over the 3-dB bandwidth of 23 GHz while the simulated input and output return losses (S11 and S22) are less than -10 dB. The IIP3 and input referred 1-dB compression point are simulated at 15 GHz and achieved +8 dBm and -6.34 dBm, respectively. The average noise figure (NF) in the entire interest band has a low value of 3.65 dB, and the DC power dissipation is only 45.63 mW. The CMOS-DA is powered by 0.9 V supply voltage. Additionally, the effect of parameters variation on performance specifications of the proposed design is simulated by Monte Carlo simulations to ensure that the desired accuracy is yielded.
In this paper, an ultra-broad bandwidth, low noise, and high gain-flatness CMOS distributed amplifier (CMOS-DA) based on a novel gain-cell is presented. The new gain-cell that enhances the output impedance as a result the gain substantially over conventional RGC is the improved version of Regulated Cascode Configuration (RGC). The new gain-cell based CMOS-DA is analyzed and simulated in the standard 0.13 μm-CMOS technology. The simulated results of the proposed CMOS-DA are included 14.2 dB average power gain with less than ± 0.5 dB fluctuations over the 3-dB bandwidth of 23 GHz while the simulated input and output return losses (S11 and S22) are less than -10 dB. The IIP3 and input referred 1-dB compression point are simulated at 15 GHz and achieved +8 dBm and -6.34 dBm, respectively. The average noise figure (NF) in the entire interest band has a low value of 3.65 dB, and the DC power dissipation is only 45.63 mW. The CMOS-DA is powered by 0.9 V supply voltage. Additionally, the effect of parameters variation on performance specifications of the proposed design is simulated by Monte Carlo simulations to ensure that the desired accuracy is yielded.
