List of Articles Process variation

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  1 - Write Error Rate Reduction Based on Thermal Effect and Dual-Vdd
  حمیدرضا زرندی Sh. Jalilian
  Write Error (WER) is one of the most drawbacks of STT-MRAM based memories. This problem usually occurred because of thermal instability and process variation. Although some methods have been proposed for WER reduction, they often did not consider the thermal effect of M More

  Write Error (WER) is one of the most drawbacks of STT-MRAM based memories. This problem usually occurred because of thermal instability and process variation. Although some methods have been proposed for WER reduction, they often did not consider the thermal effect of MTJ and had significant overhead. Therefore, proposing a new method in a lower layer of abstraction with the minimum penalty is essential. In this regard, a write driver core has been proposed, which uses two distinct ways according to the state of writing data based on the thermal feature of MTJ cell and by Dual-Vdd method. Simulation results show 11.38% write latency reduction without area and power penalty. Manuscript profile
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  2 - Proposing a Novel Write Circuit to Reduce Energy and Delay of Writing Operations in STT-MRAM Memories Using the Temperature Method
  امیرمحمد حاجی صادقی حمیدرضا زرندی Sh. Jalilian
  With the advancement of technology and the shrinking dimensions of transistors in CMOS technology, several challenges have arisen. One of the main concerns in using CMOS-based memory is the high power consumption of this type of memory. Therefore, new and non-volatile m More

  With the advancement of technology and the shrinking dimensions of transistors in CMOS technology, several challenges have arisen. One of the main concerns in using CMOS-based memory is the high power consumption of this type of memory. Therefore, new and non-volatile memories were introduced to address the shortcomings of conventional volatile memory. One of the emerging non-volatile technologies is STT-MRAM memory, an effective and efficient alternative to conventional memory such as SRAMs due to low leakage power, high density, and short access time. The positive features of STT-MRAMs make it possible to use them at different memory hierarchy levels, especially the cache level. However, STT-MRAMs suffer from high write energy. In this paper, we present a new write circuit using the temperature method; in addition to improving the high write energy, write delay is also improved. The proposed circuit lead to 22.5% and 18.62% improvement in energy and writing delay, respectively, compared to the existing methods. Manuscript profile
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  3 - Low-Error and Variation-Aware Approximate Full Adders for Imprecision-Tolerant Applications
  Mohammad Mirzaei سيامك محمدي
  In imprecision-tolerant applications such as image processing and machine learning, imprecision can be tolerated because of the nature of the application itself or the limitation of human senses. By using the approximate computation in these applications, significant po More

  In imprecision-tolerant applications such as image processing and machine learning, imprecision can be tolerated because of the nature of the application itself or the limitation of human senses. By using the approximate computation in these applications, significant power, delay, or area reductions can be achieved. In this paper, two approximate full adders and an approximate adder, with low error are proposed. The effects of die-to-die (D2D) process variation on the threshold voltage of approximate circuits have been evaluated. For evaluating the accuracy and the variability, these approximate full adders have been used and analyzed in the ripple carry adder structure, image Sharpening and image Smoothing algorithms. In terms of power-delay-product (PDP), accuracy, and area for uniformly distributed inputs, the proposed approximate full adder 1, exhibits the best performance, and the proposed approximate full adder 2 and the proposed approximate adder, show the best peak-signal-to-noise ratio (PSNR) for real images. Manuscript profile