List of Articles شبکه‌های روی تراشه

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  1 - Presenting a Multi-Criteria QoS-Aware Fault Tolerant Routing Algorithm for Network-On-Chips
  Alireza Mahjoub Fatemeh Vardi Roya Rad
  Network-on-chip is a router-based paradigm that determines the path of packet passing from the source to destination by a routing pattern through simplified protocols of the public data communication network. Sometimes, it is impossible to send packets from source to de More

  Network-on-chip is a router-based paradigm that determines the path of packet passing from the source to destination by a routing pattern through simplified protocols of the public data communication network. Sometimes, it is impossible to send packets from source to destination due to the communication problems caused by network elements in NoC such as routers and faulty links. In most cases, fault-tolerant algorithms select a reliable path using definite criteria. Therefore, in this paper, a reliable path is selected using a multi-criteria decision making technique through an adaptive approach according to the density status received from the adjacent nodes along with the path length so that when a failure occurs, a reliable path with similar QoS features is replaced by rating different paths among network nodes. The weight path selection strategy in NoCs to detect the minimal output port and multi-criteria decision making approach with VIKOR method has improvement over the basic routing algorithm in terms of delay and throughput. The algorithm hardware overhead has a reasonably low cost that maintains scalability for large scale On-Chip networks implementations. Manuscript profile
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  2 - Presenting a Network-on-Chip Mapping Approach Based on Harmony Search Algorithm
  Zahra Bagheri Fatemeh Vardi Alireza Mahjoub
  In network-on-chip implementation, mapping can be considered as an important step in application implementation. The tasks of an application are often represented in the form of a core graph. The cores establish a link between themselves using a communication platform a More

  In network-on-chip implementation, mapping can be considered as an important step in application implementation. The tasks of an application are often represented in the form of a core graph. The cores establish a link between themselves using a communication platform and often the network on the chip. For finding proper mapping for an application, developers have proposed various algorithms. In most cases, due to the complexity, exact search methods are used to find the mapping. However, these methods are suitable for networks with small dimensions. As the size of the network increases, the search time also increases exponentially. This article, from the perspective of a heuristic approach, uses the harmony search method to decide when to connect cores to routers. Our approach uses an improved version of the harmony search algorithm with a focus on reducing power consumption and delay. Algorithm complexity analysis reveals a more appropriate solution compared to similar algorithms with respect to application traffic pattern. Compared to similar methods, the algorithm achieves 39.98% less delay and 61.11% saving in power consumption. Manuscript profile