List of Articles routing algorithm

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  1 - A Fault-Tolerant Routing Algorithm for 3D Networks-on-Chip
  M.  Taghizadeh Firoozjaee M.  Taghizadeh Firoozjaee M.  Taghizadeh Firoozjaee
  The performance of Networks-on-Chip is highly dependent to the incorporated routing algorithms. In recent years, many routing algorithms have been proposed for 2D and 3D Networks-on-Chip. In 3D integrated circuits, different devices are stacked through silicon via in wh More

  The performance of Networks-on-Chip is highly dependent to the incorporated routing algorithms. In recent years, many routing algorithms have been proposed for 2D and 3D Networks-on-Chip. In 3D integrated circuits, different devices are stacked through silicon via in which the vertical connections are vulnerable to manufacturing process variations. Therefore, because of the high impact of faulty links or nodes on the performance of a Network-on-Chip, utilizing a fault-tolerant routing algorithm is of great importance especially for 3D Networks-on-Chip in which the vertical links are more vulnerable. In this paper, a new fault-tolerant routing algorithm called FT-ZXY is proposed to be used in 3D Networks-on-Chip. This routing method is capable of tolerating multiple vertical faulty links in addition to single horizontal faulty links without using any virtual channels thus incurs a very low hardware overhead. Experimental results reveal that the proposed routing algorithm has more reliability compared to the previous designs while incurs less latency and requires lower area and power overheads. Manuscript profile
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  2 - Presenting a Multi-Criteria QoS-Aware Fault Tolerant Routing Algorithm for Network-On-Chips
  Alireza Mahjoub Fatemeh Vardi Roya Rad
  Network-on-chip is a router-based paradigm that determines the path of packet passing from the source to destination by a routing pattern through simplified protocols of the public data communication network. Sometimes, it is impossible to send packets from source to de More

  Network-on-chip is a router-based paradigm that determines the path of packet passing from the source to destination by a routing pattern through simplified protocols of the public data communication network. Sometimes, it is impossible to send packets from source to destination due to the communication problems caused by network elements in NoC such as routers and faulty links. In most cases, fault-tolerant algorithms select a reliable path using definite criteria. Therefore, in this paper, a reliable path is selected using a multi-criteria decision making technique through an adaptive approach according to the density status received from the adjacent nodes along with the path length so that when a failure occurs, a reliable path with similar QoS features is replaced by rating different paths among network nodes. The weight path selection strategy in NoCs to detect the minimal output port and multi-criteria decision making approach with VIKOR method has improvement over the basic routing algorithm in terms of delay and throughput. The algorithm hardware overhead has a reasonably low cost that maintains scalability for large scale On-Chip networks implementations. Manuscript profile
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  3 - Regional Power-Aware Routing for Partially-Connected 3D Network-on-Chip
  Mitra Moalemnia HadiShahriar Shahhoseini
  Network-on-chip provides an efficient communication platform for Systems-on-chip. The static power consumption is an important issue in these networks. Switching the power supply on virtual channels during idle time is a common method for reducing the network power cons More

  Network-on-chip provides an efficient communication platform for Systems-on-chip. The static power consumption is an important issue in these networks. Switching the power supply on virtual channels during idle time is a common method for reducing the network power consumption. The traffic load at the network level and non-continuous idle period of virtual channel have caused the sources to be switched on and off continuously, which leads to increase in power consumption and other overheads. This will be more important, in partially connected 3D chip networks in which a limited number of vertical connections has been used. In this paper, a routing algorithm is proposed who employs an appropriate policy for packet distribution, and reduces the load distribution in the network and creates a continuous idle time for the resources, result in suitable power management in the network. In this routing scheme the network is divided to north and south region and some restriction applied in usage of elevators in each region and try to increase the utilization of the used resources as well as the ideal time of low traffic paths. The simulation results, derived by BookSim, show the proposed method improve the network power consumption by 18% to 30% comparing previous algorithms, and the network delay has been reduced by 32%. Manuscript profile