List of Articles junctionless

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  1 - Reducing OFF-State Current in Nano-Scale Double Gate Junctionless Field Effect Transistor (DGJL-FET) Using Doping Engineering of Channel Region
  S. Kalantari M. Vadizadeh
  Scaling the channel length leads to the increased leakage current of double gate junctionless field effect transistor (DGJL-FET) and, as a result, the increased power consumption in OFF-state. The present paper proposes a new structure for reducing the leakage current i More

  Scaling the channel length leads to the increased leakage current of double gate junctionless field effect transistor (DGJL-FET) and, as a result, the increased power consumption in OFF-state. The present paper proposes a new structure for reducing the leakage current in DGJL-FET, which is called modified DGJL-FET. In this structure, the channel doping under the gate is the same as the drain and source doping but higher than the mid-channel doping. The simulation results indicated that reducing the thickness of the doped layer under the gate, D, resulted in the reduced OFF-state current. For the proposed device with 10 nm channel length, the OFF-state current is less than that in the regular DGJL-FET by two orders of magnitude. Performance of the regular DGJL-FET and modified DGL-FET for different channel lengths is compared based on the IOFF/ION ratio, sub-threshold slope (SS), and intrinsic gate delay. For modified DGJL-FET, the mid-channel doping and Dare considered as additional parameters for improving the device’s performance in nanometer regime. The simulation results indicated that in the proposed device with channel length of 15 nm, values of SS and IOFF/ION ratio are improved compared to the regular DGJL-FET by 14% and 106 orders of magnitude, respectively. Manuscript profile
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  2 - Improvement in Electrical Characteristics of Silicon on Insulator Junctionless Field Effect Transistor (SOI-JLFET) Using the Auxiliary Gate
  M. Vadizadeh
  Silicon on insulator junctionless field effect transistor (SOI-JLFET) includes a single type doping at the same level in the source, channel, and drain regions. Therefore, its fabrication process is easier than inversion mode SOI-FET. However, SOI-JLFET suffers from hig More

  Silicon on insulator junctionless field effect transistor (SOI-JLFET) includes a single type doping at the same level in the source, channel, and drain regions. Therefore, its fabrication process is easier than inversion mode SOI-FET. However, SOI-JLFET suffers from high subthreshold slope (SS) as well as high leakage current. As a result, the SOI-JLFET device has limitation for high speed and low power applications. For the first time in this study, use of the auxiliary gate in the drain region of the SOI-JLFET has been proposed to improve the both SS and leakage current parameters. The proposed structure is called "SOI-JLFET Aug". The optimal selection for the auxiliary gate work function and its length, has improved the both SS and ION/IOFF ratio parameters, as compared to Regular SOI-JLFET. Simulation results show that, SOI-JLFET Aug with 20nm channel length exhibits the SS~71mV/dec and ION/IOFF~1013. SS and ON-state to OFF-state current (ION/IOFF) ratio of SOI-JLFET Aug are improved by 14% and three orders of magnitudes, respectively, as compared to the Regular SOI-JLFET. The SOI-JLEFT Aug could be good candidate for digital applications. Manuscript profile
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  3 - Modeling a Proposed Nanoscale SOI-Junctionless for Improvement of Steady-State and Frequency Characteristics
  Mohammad Kazem Anvarifard
  In this paper in order to improve the electrical performance of nanoscale SOI-junctionless, a targeted modification has been performed. The proposed structure has been aimed to reduce the OFF current and self-heating effect. To reduce the self-heating effect, the buried More

  In this paper in order to improve the electrical performance of nanoscale SOI-junctionless, a targeted modification has been performed. The proposed structure has been aimed to reduce the OFF current and self-heating effect. To reduce the self-heating effect, the buried oxide thickness has been reduced into the half and a part of it has been replaced by a buffer layer. Increase in the thermal conduction and making an extra depletion layer in the buffer layer/channel region interface are led to improvement of the electrical performance in the terms of DC and AC. In the proposed method, which is based on the energy band modification, the parameters such as IOFF, ION/IOFF, subthreshold swing, lattice temperature, voltage gain, transconductance, parasitic capacitances, power gains, cut-off frequency, maximum oscillation frequency and minimum noise figure have been improved. Also, a designing consideration for the role of buffer layer on the proposed device has been performed. Comparing structures under the study simulated by the SILVACO showed the electrical performance superiority for the proposed device. Manuscript profile
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  4 - Design and Simulation of a Lable-Free Nano Biosensor for Detecting Molecules via Nanotube Junctionless Field Effect Transistor
  Zahra Ahangari
  Biosensors have various applications especially in medical diagnosis. In this paper, nanotube junctionless transistor is employed for label-free detection of biomolecules. The proposed device works based on dielectric modulated principle. In this transistor, the gate vo More

  Biosensors have various applications especially in medical diagnosis. In this paper, nanotube junctionless transistor is employed for label-free detection of biomolecules. The proposed device works based on dielectric modulated principle. In this transistor, the gate voltage is responsible for controlling the drain current and in case of gate capacitance variation, the drain current can be modulated. A nanogap is embedded in the gate insulator region for immobilization of biomolecules. Since each individual biomolecule has its specific dielectric constant, the accumulation of different biomolecule in the nanogap changes the dielectric constant of the nanogap, which eventually leads to the variation of gate capacitance and the drain current. Threshold voltage variation and drain current modulation are considered as two measures for detecting biomolecules and determining the biosensor’s sensitivity. The proposed device has two internal and external gates with low static power consumption as well as simpler low temperature fabrication process. One of the main advantages of the proposed device is its high selectivity and sensitivity, especially for biomolecules with low dielectric constant. Impact of critical physical and structural design parameters on the operation of the biosensor are thoroughly investigated. Gate workfunction and channel doping density are two critical parameters that affect the sensitivity of the biosensor and as a consequence, optimum values should be determined for them. Due to the low power consumption and high sensitivity, this sensor can be considered as a potential candidate for applications in nanoscale regime. Manuscript profile