Design of Low Power High Speed Dilation Operator for Binary Images in CMOS Technology
Subject Areas : electrical and computer engineering
M. hajirahimi
1
,
E. Kabir
2
,
3
1 - Tarbiat Modares University
2 - Tarbiat Modares University
3 -
Keywords: ASICCMOShybrid wave-pipeline structurereal time image processingmorphologydilationbinary image,
Abstract :
This paper describes the design of hybrid wave-pipeline architecture for implementation of real time morphological dilation. With minor changes to this architecture, it can be utilized for erosion, closing, and opening operators. The new architecture results in higher speed, less hardware complexity, and lower area and power dissipation compared to conventional pipeline implementation. In addition, it is faster than the wave-pipeline structure, without the difficulty of balancing the delay of long signal paths. Using the new architecture, three ASIC chips in 0.18µm CMOS are designed for binary image processing through Verilog. These chips dilate a 1024×1024 image by a 21×21 structuring element in 256.58μ s. The maximum frequency of the operations is 5.882 GHz, 5 GHz, and 4.167 GHz. For the power supply of 1.8 V and the 4.167 GHz frequency, the power dissipation is 597mW, 478 mW, and 410 mW, and the chip area is 0.118 mm2, 0.087 mm2, and 0.075 mm2, respectively.
[1]R. C. Gonzalez and R. E. Woods, Digital Image Processing, 2nd ed. Prentice-Hall, 2002.
[2]M. Duff, "Parallee processor for digital image processing," in Advances in Digital Image Processing. P. Stucki, Ed. New York: Plenum, pp. 265-279, 1979.
[3]K. E. Batcher, "Design of a massively parallel processor," IEEE Trans. Comput., vol. 29, no. 9, pp. 836-840, Sep. 1980.
[4]S. Wilson, "The pixie-5000_a systolic array processor," in Proc. IEEE Comput. Soc. Workshop Comp. Architecture for Pattern Analysis and Image Database Management, pp. 477-483, Miami Beach, FL, Nov. 1985.
[5]M. J. Kimmel, R. S. Jaffe, J. R. Mandeville, and M. A. Lavin, "MITE: morphic image transform engine, an architecture for reconfigurable pipelines of neighborhood processor," in Proc. IEEE Comput. Soc. Workshop Comp. Architecture for Pattern Analysis and Image Database Management, Miami Beach, FL, pp. 493-500, Nov. 1985.
[6]E. W. Kent and S. L. Tanimoto, "Hierarchical cell logic and the PIPE processor: structural and functional correspondence," in Proc. IEEE Comput. Soc. Workshop Comp. Architecture for Pattern Analysis and Image Database Management, Miami Beach, FL, pp. 311-319, Nov. 1985.
[7]R. M. lougheed, D. L. McCubbrey, and S. R. Sternberg, "Cyto computer: architectures for parallel image processing," in Proc. of the Workshop on Picture Data Description and Management, Asilomar, CA, pp. 281-286, Aug. 1980.
[8]A. C. P. Loui, A. N. Venetsanopoulos, and K. C. Smith, "Flexible architecture for morphological image processing and analysis," IEEE Trans. on Circuit and System for Video Technology, vol. 2, no. 1, pp. 72-83, Mar. 1992.
[9]E. N. Malamas and A. G. Malamos, "Fast implementation of binary morphological operations on hardware -efficient systolic architectures," J. of VLSI Signal Processing, vol. 25, no. 1, pp. 79-93, May 2000.
[10]B. Gatos and S. J. Perantons, "Fast implementation of morphological operations using binary image block decomposition," Int. J. of Image and Graphics, vol. 4, no. 2, pp. 1-21, Dec. 2004.
[11]H. Hedberg, F. Kristensen, P. Nilsson, and V. Owall, "A low complexity architecture for binaryimage erosion and dilation using structuring element decomposition," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol. 4, pp. 3431-3434, May 2005.
[12]J. Nyathi and J. G. Delgado-Frias, "A hybrid wave pipelined network router," IEEE Trans. on Circuits and Systems-I: Fundamental Theory and Applications, vol. 49, no. 12, pp. 1764-1772, Dec. 2002.
[13]J. Lowe, A High-Performance, Hybrid Wave-Pipelined Linear Feedback Shift Register with Skew Tolerant Clocks , MS. Thesis, Washington State University Schoolof Electrical Engineering and Computer Science, Aug. 2004.
[14]S. B. Tatapudi and J. G. Delgado-Frias, "A pipelined multiplier using a hybrid wave-pipelining scheme," in Proc.Intl. Conf. Computer Design (CDES), pp. 191-197, Jun. 2005.
[15]S. B. Tatapudi and J. G. Delgado-Frias, "A high performance hybrid wave-pipelined multiplier," in Proc. of the IEEE Computer Society Annual Symp on VLSI, New Frontiers in VLSI Design, pp. 282-283, 11-12 May 2005.
[16]م. حاجی رحیمی، ا. کبیر و ع. نبوی، طراحی و پیاده سازی دو ساختار خط لوله ای تموجی ترکیبی سریع برای فراخش مورفولوژی، " دومین کنفرانس بین المللی انجمن ایران، تهران، دانشگاه شهید بهشتی،صص2496-2500،اسفند 1385.
[17]R. M. Haralic, S. R. Sternberg, and X. Zhuang, "Image analysis using mathematical morphology," IEEE Trans. Pattern Anal. Machine Intell., vol. 9, no. 4, pp. 532-550, Jul. 1987.
[18]J. Serra, Image Analysis and Mathematical Morphology, New York: Academic Press, 1982.
[19]F. Y. C. Shih and O. R. Mitchell, "Threshold decomposition of gray scale morphology into binary morphology," IEEE Trans. Pattern Anal. Machine Intell., vol. 11, no. 1, pp. 31-42, Jan. 1989.
[20]W. P. Burleson, M. Ciesielski, F. Klass, and W. Liu, "Wave-pipelining: a tutorial and research survey," IEEE Trans. on VLSI Systems, vol. 6, no. 3, pp. 464-474, Sep. 1998.
[21]م.حاجی رحیمی، طراحی تراشهASIC برای عملیات بی درنگ مورفولوژی در پردازش تصویر، پایان نامه کارشناسی ارشد،دانشگاه تربیت مدرس، بخش مهندسی برق پاییز 1385.
[22]م. حاجی رحیمی، ا. کبیر و ع. نبوی، طراحی کم توان ASICبرای عملگر فراخش در پردازش تصویر دودویی، " چهارمین کنفرانس ماشین بینایی و پردازش تصویر ایران(MVIP2007)، دانشگاه فردوسی مشهد،صص470-477،بهمن 1385.
[23]M. Hajirahimi, A. Nabavi, and E. Kabir, "A low-power high-speed architecture for binary morphological dilation using hybrid wave pipeline," Accepted in the International Conf. on Information Sciences, Signal Processing and its Applications (ISSPA 2007).
