يک مدل سطح بالا برای وارسی خواص CTL در طرح توصيف شده توسط VHDL
محورهای موضوعی : مهندسی برق و کامپیوتربيژن عليزاده 1 , زین العابدین نوابی 2
1 - دانشگاه تهران
2 - دانشگاه تهران
کلید واژه: توابع انتقال حالتحلکننده معادلات صحيحمعادلات چندجملهای با متغيرهای صحيحBDD و Boolean Satisfiability ,
چکیده مقاله :
در اين مقاله قصد داريم مدل سطح بالايي بر پاية معادلات چندجملهاي با متغيرهاي صحيح ارائه دهيم كه مناسب براي وارسي خواص بر پاية CTL (Computational Temporal Logic) ميباشد. اكثر ابزارهاي وارسي از ساختمان دادههاي سطح پاييني مانند BDD استفاده ميكنند و اين ساختمان دادهها به علت نياز به حافظه زياد، قابل اعمال به بخش مسير داده از يك طرح نميباشند، در حالي كه مدل سطح بالاي پيشنهادی در اين مقاله قادر است بخشهاي مسير داده و كنترلر را با هم مورد ارزيابي قرار دهد. ضمن اينكه روش پيشنهادي به گونهاي است كه نياز به حل صريح معادلات نميباشد و اين كار توسط عمليات جايگزيني و سادهسازي انجام ميگيرد. در انتها نتايج كارمان با ابزار VIS، بعنوان يك ابزار وارسي بر پاية BDD، مقايسه ميگردند.
This paper describes the use of polynomial integer equations for high level model of digital circuits for property checking formal verification at this level. Most formal verification methods use low-level representations of a design like BDDs. BDD operations are not applicable to a large datapath because of large CPU time and memory usage. In our method, a behavioral state machine is represented by a list of integer equations, and RT level properties are directly applied to this representation. Furthermore, this method is applied to circuits without having to separate their data and control sections. For this implementation, we use a canonical form of integer equations, which simplifies equations instead of solving them. This paper compares our results with those of the VIS verification tool that is a BDD based program
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