A New Calibration Method for SAR Analog-to-Digital Converters Based on All Digital Dithering
محورهای موضوعی : Signal Processing
Ebrahim Farshidi
1
(Chamran University)
Shabnam Rahbar
2
(Shahid Chamran University )
کلید واژه: SAR , Converter , Calibration , Perturbation , Radix-2 , DNL and INL,
چکیده مقاله :
In this paper a new digital background calibration method for successive approximation register analog to digital converters is presented. For developing, a perturbation signal is added and also digital offset is injected. One of the main advantages of this work is that it is completely digitally and eliminates the nonlinear errors between analog capacitor and array capacitors due to converter’s capacitors mismatch error by correcting the relative weights. Performing of this digital dithering method does not require extra capacitors or double independent converters and it will eliminate mismatches caused by these added elements. Also, No extra calibration overhead for complicated mathematical calculation is needed. It unlike split calibration, does not need two independent converters for production of two specified paths and it just have one capacitor array which makes it possible with simple architecture. Furthermore, to improve DNL and INL and correct the missing code error, sub radix-2 is used in the converter structure. Proposed calibration method is implemented by a 10 bit, 1.87-radix SAR converter. Simulation results with MATLAB software show great improvement in static and dynamic characteristics in applied analog to digital converter after calibration. So, it can be used in calibration of successive approximation register analog to digital converters.
In this paper a new digital background calibration method for successive approximation register analog to digital converters is presented. For developing, a perturbation signal is added and also digital offset is injected. One of the main advantages of this work is that it is completely digitally and eliminates the nonlinear errors between analog capacitor and array capacitors due to converter’s capacitors mismatch error by correcting the relative weights. Performing of this digital dithering method does not require extra capacitors or double independent converters and it will eliminate mismatches caused by these added elements. Also, No extra calibration overhead for complicated mathematical calculation is needed. It unlike split calibration, does not need two independent converters for production of two specified paths and it just have one capacitor array which makes it possible with simple architecture. Furthermore, to improve DNL and INL and correct the missing code error, sub radix-2 is used in the converter structure. Proposed calibration method is implemented by a 10 bit, 1.87-radix SAR converter. Simulation results with MATLAB software show great improvement in static and dynamic characteristics in applied analog to digital converter after calibration. So, it can be used in calibration of successive approximation register analog to digital converters.
[1] F. Kuttner, “A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13- m CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2002.#
[2] J. Craninckx and G. Van der Plas, “A 65 fJ/conversion-step 0-to-50 MS/s 0-to-0.7 mW 9 b charge-sharing SAR ADC in 90 nm digital CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2007.#
[3] V. Giannini et al., “An 820 W 9 b 40 MS/s noise-tolerant dynamic-SAR ADC in 90 nm digital CMOS,” in IEEE ISSCC Dig. Tech.Papers, Feb. 2008.#
[4] C. C. Liu et al., “A 10 b 100 MS/s 1.13 mW SAR ADC with binary scaled error compensation,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2010.#
[5] Y. Z. Lin et al., “A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2010.#
[6] C. C. Liu et al., “A 1 V 11 fJ/conversion-step 10 bit 10 MS/s asynchronous SAR ADC in 0.18 m CMOS,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2010.#
[7] G. Promitzer, “12 bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1 MS/s,” IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1138–1143, Jul. 2001.#
[8] C. P. Hurrell et al., “An 18 b 12.5 MHz ADC with 93 dB SNR,” in EEE ISSCC Dig. Tech. Papers, Feb. 2010.#
[9] W. Liu, P. Huang, and Y. Chiu, “A 12 b 22.5/45 MS/s 3.0 mW 0.059 mm CMOS SAR ADC achieving over 90 dB SFDR,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2010.#
[10] S. M. Louwsam et al., “A 1.35 GS/s, 10 b, 175 mW time-interleaved AD converter in 0.13 m CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 778–786, Apr. 2008.#
[11] B. E. Amazeen, M. C. W. Coln, and G. R. Carreau, ”Quasi-differential successive-approximation structures and methods for converting analog signals into corresponding digital signals.” U.S. Patent 6,400,302, June,2002.#
[12] W. Liu, Y. Chang, S.-K. Hsien, B.-W. Chen, Y.-P. Lee, W.-T. Chen, T.-Y. Yang, G.-K. Ma, and Y. Chiu, ”A 600MS/s 30mW 0:13_m CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization,” ISSCC2009 Digest of Technical Papers, vol. 52, 2009, pp. 82-83.#
[13] W. Liu and Y. Chiu, “An equalization-based adaptive digital background calibration technique for successive approximation analog-to-digital converters,” in ASIC, 2007. ASICON'07. 7th International Conference on, pp. 289-292, 2007.#
[14] P. Harpe, H. Hegt, and A. Roermund, Smart AD and DA Conversion: Springer, 2010.#
[15] W. Liu, P. Huang, and Y. Chiu, “A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration,” IEEE Journal of Solid-State Circuits, vol. 46, pp. 2661-2672, 2011.#
[16] R. Xu, B. Liu, and J. Yuan, “Digitally Calibrated 768-kS/s 10-b Minimum-Size SAR ADC Array With Dithering,” IEEE Journal of Solid-State Circuits, vol. 47, pp. 2129-2140, 2012.#
[17] S. Rahbar and E. Farshidi “Digital Background Calibration of Radix 1.83 Successive Approximations Register Analog-to-Digital Converter using the Split Architecture,” Technical Journal of Engineering and Applied Sciences, vol. 3, no. 2, pp. 233-238, 2013.#
[18] J. A. McNeill, K. Y. Chan, M. C. W. Coln, C. L. David, and C. Brenneman, “All-Digital Background Calibration of a Successive Approximation ADC Using the Split ADC Architecture,” Circuits and Systems I: IEEE Transactions on Regular Papers, vol. 58, pp. 2355-2365, 2011.#
[19] L. Du, N. Ning, S. Wu, and Y. Liu, “A digital background calibration technique for SAR ADC based on capacitor swapping,” IEICE , vo11, no. 12, pp. 1-11, 2014.#
[20] J. Wu, A. Wu, and Y. Du, “Dithering-based calibration of capacitor mismatch in SAR ADCs,” Electronic Letters IET, vol. 52, no. 19, pp. 1198-1600, 2016.#
