طراحی مدارهای مالتی‌پلکسر و دی‌مالتی‌پلکسر کوانتومی برگشت‌پذیر سه‌مقداری
محورهای موضوعی : مهندسی برق و کامپیوترمجید حق پرست 1 , اسماء طاهری منفرد 2
1 - دانشگاه آزاد اسلامی واحد شهرری
2 - دانشگاه آزاد اسلامی واحد آبادان
چکیده مقاله :
مدارهای مالتی‌پلکسر و دی‌مالتی‌پلکسر از اساسی‌ترین مدارها در ساخت سخت‌افزارهای پیچیده به شمار می‌آیند و بنابراین افزایش کارایی آنها اهمیت بسیاری دارد. یکی از مواردی که در سال‌های اخیر توجه محققان را به خود جلب کرده است طراحی مدارهایی با توان پایین است. استفاده از منطق برگشت‌پذیر در طراحی مدار باعث کاهش اتلاف توان و کاهش توان مصرفی آن می‌شود و همچنین استفاده از منطق سه‌مقداری نیز باعث کارایی بهتر، کاهش توان مصرفی و افزایش تحمل‌پذیری اشکال در مدارهای برگشت‌پذیر می‌گردد. در این مقاله مدارهای مالتی‌پلکسر و دی‌مالتی‌پلکسر کوانتومی برگشت‌پذیر سه‌مقداری را ارائه داده‌ایم و در طراحی آنها از دروازه‌های برگشت‌پذیر سه‌مقداری Controlled Feynman و Shift استفاده کرده‌ایم. مدارهای ارائه‌شده در این مقاله در مقایسه با طرح‌های پیشین عملکرد بهتری دارد و مقدار بهبود گزارش شده است.
Multiplexer and demultiplexer circuits are among the main circuits in designing the complicated hardware. Therefore, enhancing their performance is very important. In the last few years one of the cases that got the attention of the researchers is designing circuits with low power. Using the reversible logic in designing the circuits can reduce power dissipation and power consumption. Using the ternary logic also leads to a better performance, reducing the power consumption and enhancing of fault tolerance in reversible circuits. In this paper, we have presented quantum reversible ternary multiplexer and demultiplexer circuits, we have used reversible ternary shift and controlled Feynman gates. Presented circuits in this paper have a better performance in compared to the previous designs. The improvements are reported.
[1] R. Landauer, "Irreversibility and heat generation in the computing process," IBM J. Research and Development, vol. 5, no. 3, pp. 183-191, Jul. 1961.
[2] C. H. Bennett, "Logical reversibility of computation," IBM J. Research and Development, vol. 17, no. 6, pp. 525-532, Nov. 1973.
[3] P. Kerntopf, M. A. Perkowski, and M. H. A. Khan, "On universality of general reversible multiple valued logic gates," in Proc. IEEE 34th Int. Symp. Multiple Valued Logic, ISMVL'04, pp. 68-73, May 2004.
[4] M. Perkowski, et al. "A general decomposition for reversible logic," in Proc. RM'2001, Starkville, pp. 119-138, Aug. 2001.
[5] M. Perkowski and P. Kerntopf, "Reversible logic. invited tutorial," in Proc. Euro-Micro, 7 pp., Sept. 2001.
[6] G. Schrom, Ultra-Low-Power CMOS Technology, Ph.D Thesis, Technischen Universitat Wien, 1998.
[7] R. C. Merkle, "Two types of mechanical reversible logic," Nanotechnology, vol. 4, no. 2, pp. 114-131, Apr. 1993.
[8] D. Miller and M. Thornton, Multiple Valued Logic: Concepts and Representations, Morgan and Claypool Publishers, 2008.
[9] A. T. Monfared and M. Haghparast, "Design of new quantum/reversible ternary subtractor circuits," J. of Circuits, Systems and Computers, vol. 25, no. 2, 8 pp., Feb. 2016.
[10] P. Houshmand and M. Haghparast, "Design of a novel quantum reversible ternary up-counter," International J. of Quantum Information, vol. 13, no. 5, 13 pp., Aug. 2015.
[11] A. T. Monfared and M. Haghparast, "Design of novel quantum/reversible ternary adder circuits," International J. of Electronics Letters, vol. 5, no. 2, pp. 149-157, Apr. 2017.
[12] M. Haghparast and A. T. Monfared, "Novel quaternary quantum decoder, multiplexer and demultiplexer circuits," International J. of Theoretical Physics, vol. 56, no. 5, pp. 1694-1707, May 2017.
[13] A. T. Monfared and M. Haghparast, "Designing new ternary reversible subtractor circuits," Microprocessors and Microsystems, vol. 53, pp. 51-56, Aug. 2017.
[14] M. H. A. Khan, "Design of reversible quantum ternary multiplexer and demultiplexer," Engineering Letters, vol. 13, no. 3, pp. 65-69, Sept. 2006.
[15] R. Parvin Zadeh and M. Haghparast, "A new reversible/quantum ternary comparator," Australian J. of Basic and Applied Sciences, vol. 5, no. 12, pp. 2348-2355, Dec. 2011.
[16] M. Nielsen and I. Chuang, Quantum Computation and Quantum Information, Cambridge University Press, 2000.
[17] M. H. A. Khan and M. A. Perkowski, "Quantum ternary parallel adder/subtractor with partially-look-ahead carry," J. of Systems Architecture, vol. 53, no. 7, pp. 453-464, Jul. 2007.
[18] A. Muthukrishnan and C. R. Stroud Jr, "Multi-valued logic gates for quantum computation," arXiv:quant-ph/0002033, 8 pp., Oct. 2000.
[19] A. T. Monfared and M. Haghparast, "Novel design of quantum/reversible ternary comparator circuits," J. of Computational and Theoretical Nanoscience, vol. 12, no. 12, pp. 5670-5673, Dec. 2015.
