آنالیز و گسترش مدل فشرده زمان تأخیر انتشار گیت‌های NAND فناوری CMOS نانومتری در مقابل تغییرات آماری فرآیند ساخت
الموضوعات :
حامد جوي‌پا
1
(دانشگاه کاشان)
داریوش دیدبان
2
(دانشگاه کاشان)
الکلمات المفتاحية: تغییرات آماری زمان تأخیر انتشار ضریب همبستگی, گیت NAND مدل اتمیستیک,
ملخص المقالة :
با کوچک‌شدن ابعاد ترانزیستور در مقیاس نانومتری، پارامترهای الکتریکی ترانزیستور دچار تغییرات آماری یا تصادفی می‌شوند و از طرفی تخمین دقیق تغییرات این پارامترها توسط شبیه‌سازهای اتمیستیک بسیار وقت‌گیر و هزینه‌بر است. در این مقاله برای اولین بار از مدل‌های تحلیلی جهت بررسی تأثیر تغییرات آماری فرایند ساخت بر پارامتر تأخیر انتشار یک گیت NAND در فناوری 35 نانومتری CMOS استفاده شده است. به عبارت دیگر با انتخاب دسته مناسبی از پارامترهای مدل تحلیلی، اثر تغییرات آماری بر روی زمان تأخیر انتشار، مورد مدل‌سازی و گسترش قرار گرفته است. همچنین مدل تحلیلی مورد استفاده در برابر تغییرات آماری فرایند ساخت صحت‌سنجی شده و با شبیه‌سازی‌های دقیق اتمیستیک مقایسه گردیده است. اگرچه مقادیر میانگین تأخیر انتشار در اثر انتخاب دسته پارامترهای آماری مختلف، حداکثر خطای 7/8% را در مقایسه با شبیه‌سازی‌های دقیق اتمیستیک ایجاد می‌نماید اما با اعمال رهیافت پیشنهادی می‌توان تا دقت 4/3%، انحراف معیار زمان تأخیر انتشار را در مقایسه با مدل اتمیستیک پیش‌بینی کرد. همچنین با بازتولید نرمال پارامترها، خطای انحراف معیار به 9/9% می‌رسد که در نهایت با پیشنهاد الگوریتم بازتولید نرمال پارامترها با لحاظ ضریب همبستگی، خطای انحراف معیار به 6/1% کاهش می‌یابد.
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